so I've been trying to solve some questions in the book Free Range VHDL. The question I have problems with is:
Provide a VHDL behavioral model of the D flip-flop. The S and R inputs are an active low asynchronous preset and clear. If both the S and R inputs are asserted simultaneously, the output of the flip-flop will toggle.
My code is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sds is
Port ( d,clk,s,r :in std_logic;
f: out STD_LOGIC);
end sds;
architecture Behavioral of sds is
signal sr: std_logic_vector(1 downto 0);
signal outs : std_logic;
begin
sr <= s & r; --concatenating set and reset
process(clk,sr)
begin
case sr is
when "00" => outs <= not outs; --should toggle when both set and reset are 0
when "01" => outs <= '1'; --output should be 1 when set is 0
when "10" => outs <= '0'; --output should be zero when set is 1 and reset is 0
when "11" => if rising_edge(clk) then outs <= d; --classic d flip flop
end if;
when others => outs <= '0';
end case;
end process;
f <= outs;
end Behavioral;
The code works fine on my FPGA except for the toggling part. I cannot make the output toggle when both set and reset are 0. It always produces 1. Where is my mistake in the code? Thank you all.
