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Does SystemVerilog contain a feature whereby it is able to detect what program is compiling the code (for synthesis or simulation) and then include or exclude sections of file for processing?

This feature could be used to declare "simulation only" code blocks and also write portable code whereby a design block instantiates different IP depending on wheather it is being compiled by Quartus, Libero or some other FPGA compiler.

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  • \$\begingroup\$ This feature has been introduced into VHDL 2019 as "Conditional analysis tool directives" \$\endgroup\$ – Quantum0xE7 Aug 30 '20 at 12:56
  • \$\begingroup\$ Usual way would just be generate depending on a parameter passed to the compiler, or an ifdef. \$\endgroup\$ – awjlogan Aug 30 '20 at 13:10
  • \$\begingroup\$ In VHDL a limited form has always been available as some variation of -- pragma translate off (and on) if you merely need to distinguish between synthesis (obeys the pragma) and simulation (does not). I'd expect something similar in Verilog surely? Extending to different synth tools ... no. But you can pass a different value to a generic from different synthesis scripts, and "if ... generate" or use configurations. \$\endgroup\$ – Brian Drummond Aug 30 '20 at 13:13
  • \$\begingroup\$ VHDL has generate and pragma, but it is not enough to create truly portable code. If we have a VHDL block that contains IP from two different VHDL vendors and want to be able to compile it across both vendors, it is impossible since each vendor does not identity the IP component of the other vendor. It does not matter if I use generate or pragma. \$\endgroup\$ – Quantum0xE7 Aug 31 '20 at 14:22
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Yes, it is called the conditional compile construct `ifdef or `ifndef. For examples

module foo(...);

`ifdef SYNTHESIS
  // code to be synthesised
`else
  // code not to be synthesized
`endif

endmodule
 

See https://stackoverflow.com/questions/58996919/how-to-determine-that-synthesis-is-done-in-quartus

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  • \$\begingroup\$ yes but this is not sufficient, can systemverilog find out which tool is compiling or simulating the code i.e the tool name and version number? \$\endgroup\$ – Quantum0xE7 Aug 31 '20 at 14:23
  • \$\begingroup\$ The link I provided in my answer shows quartus providing the tool name for synthesis. But you would have to know the tool name in advance. Your command line scripts could easily provide generic tool name and version definitions. \$\endgroup\$ – dave_59 Aug 31 '20 at 15:08

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