In the schematic of fine delay, each unit should produce 3ps delay, so the fine delay block is constructed using parallel combination of 8 inverters... Like that parallel combination of inverters we have 2 structures. To one structure we applied the signal which is to be fine delayed. To another structure we applied the signal which is delayed by 24ps.

So here in this structure how is fine delaying happening and how is phase interpolation happening?

Image shows the architecture

  • \$\begingroup\$ You probably need to look inside each inverter, to see how it is implemented, to answer this question. \$\endgroup\$ – Brian Drummond Aug 31 at 13:40

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