The working logic of CMOS inverter

Below is a CMOS circuit for an inverter (or NOT gate). According to the book I am reading, when $$\V_{x} = V_{supply}\$$, $$\T_{1}\$$ will be turned off and $$\T_{2}\$$ will be turned on. So $$\T_{2}\$$ will pull the output $$\V_{f}\$$ down to 0.

But I have been wondering, since $$\T_{1}\$$ is turned off, there will be no current from $$\V_{supply}\$$ through $$\T_{1}\$$ to $$\V_{f}\$$. If I consider $$\T_{1}\$$ as a resistor, there will be no voltage drop through it. So why $$\V_{f}\$$ choose to be 0 rather than $$\V_{supply}\$$ ? I guess I missed some important concept.

When a logic $$\V_x = 1\$$ is applied to both transistors' gates, T2 has sufficient $$\V_{GS}\$$ to form a minority inversion channel, whereas T1 won't (MOS will be in accumulation). You can think the channel to electrically connect the Source and Drain terminals: a sort of short between them.
Now, if T2 has its source at ground, such connection will take $$\V_f\$$ to ground as well -- namely acting as a what's usually called a PDN. T2 will be in triode with $$\V_{DS}=0\$$ and this agrees with $$\I_{DS} = 0\$$. Also notice that T2 will be working on its highest VTC, thus capable to sink the largest current. T1 will be in cut-off and will be working on its lowest VTC, even though $$\V_{SD} = V_{supply}\$$.