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I am designing an anti-aliasing filter for an MCP3202 ADC. I'm kind of confused by defining my corner frequency Fc, I'm working with a 60 Hz input signal with harmonics until around 3 kHz that comes from an air conditioner current signal, so I can say that the maximum frequency of my input signal is 3 kHz or 50 X 60 Hz.

The MCP3202 is a SAR ADC, with SPI output protocol, 0-5 Vdd, and its specification says "100kSps", that requires an input clock signal Fclk more or less of 1.8MHz, that is, to generate a sample it needs a clock signal of 18 X Fclk, supplied by a microcontroller.

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As we know SAR ADC works with the "sample and hold" method to hold the samples and be converted. I assumed that the internal R-C input of the ADC works with the ADC clock frequency Fclk, which generates my confusion because the output of the anti-aliasing filter is wired to the ADC (no bucket filter before the ADC,) so the filter "sees" the Fclk in the ADC's input.

Being more specific according to this information.

Does the cutoff frequency Fc have to be defined by the clock frequency Fclock if not, is Fc defined by the sampling frequency specified in the ADC datasheet (100 kSps?)

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    \$\begingroup\$ It is defined by the sampling rate, so 100khz if you run at maximum. \$\endgroup\$ Sep 1, 2020 at 23:44
  • \$\begingroup\$ "harmonics until around 3 kHz that comes from an air conditioner current signal, so I can say that the maximum frequency of my input signal is 3 kHz or 50 X 60 Hz." Harmonics are normally like 3,5,7. I know no other application than ADC characterization with special setups where one uses harmonics more than 7 (or some clever tx/rx stuff e.g. for mobile phones). What you see in the 3khz range is probably feedback distortion from the air conditioner motor. So If you want to measure the current, I would stick with a 60 Hz filter or lets say 100Hz \$\endgroup\$
    – schnedan
    Sep 9, 2020 at 7:59
  • \$\begingroup\$ @schnedan Hi Schnedan, thanks for your feedback. this criterion was established based in an IEEE paper ("Dynamic Performance of Air Conditioners with Variable Frequency Drive"), they say that after the 50th harmonic the current doesn't have any impact, but I set up the cut frequency of my filter in 1.5kHz due to the samp rate that I could achieve with a microcontroller used for reading proposes. Thanks for your help. \$\endgroup\$ Sep 9, 2020 at 21:57
  • \$\begingroup\$ any practical comment is appreciated, I'm passing to practical implementations after just being in theoretical analysis in the university. :) \$\endgroup\$ Sep 9, 2020 at 21:58
  • \$\begingroup\$ @joshuaandresblancojerez - would be great if you can publish a osciliscope shot of that current signal - or even better the spectrum. I am really curious what impact a 50th harmonic should have. \$\endgroup\$
    – schnedan
    Sep 9, 2020 at 22:34

3 Answers 3

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The MCP3202 has an on-chip sample and hold. Don't make assumptions about internal RCs that work at the Fclk frequency.

You can ignore Fclk, as this is an 'implementation detail' of the ADC. It's important if you're programming Fclk, it's irrelevant if you simply want to use the ADC at whatever rate Fclk sets it to.

The ADC has a maximum sample rate of 100 kS/s, but you can choose a lower rate if you don't want to handle that throughput.

You want to process signals up to 3 kHz. By Nyquist, that means you need an absolute minimum rate of 6 kS/s, at which you would need an unfeasibly good AA filter. To work with a practical AA filter, you need a somewhat higher sampling rate.

You need to know how you are going to be processing the results of your ADC measurements before you design the AA filter.

Are you going to do frequency selective analysis digitally? In this case you only need the AA filter to protect your samples from aliasing. For instance with a 10 kS/s sample rate, the AA filter would have to pass 0-3 kHz, and stop 7 kHz and above. This allows a very generous transition band, making it easier to design. For instance, any noise at 6 kHz that gets aliased to 4 kHz will be ignored by your subsequent analysis stopping at 3 kHz.

Alternatively, do you want every sample taken by your ADC to be valid as it is without further analysis? In this case with 10 kS/s sampling, your AA filter should pass 0-3 kHz, and stop at least 5 kHz (Nyquist) and above. However it will be beneficial to stop from as close as possible to 3 kHz as it can to remove as much noise above 3 kHz as possible. This then gives you a filter flatness/size/performance tradeoff.

You'll notice that in neither case do we use the Nyquist rate directly to specify the AA filter, but via the input bandwidth, and the sort of analysis we want to do subsequently.

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  • \$\begingroup\$ Thank you for sharing your knowledge and precise answer. Answering the questions... I'm not doing a frequency selective analysis, is about just get the samples for calculating the True-RMS value with an ATMEGA328P, so I need a "reliable" amplitude measurement, with a sample rate of 12kS/s, I already made the tests(I think I'm having a small transition band for an acceptable settlement with 60db/dec or 80 db/dec and be the most accurate as possible with that ADC if you have some advice I'll appreciate it). t \$\endgroup\$ Sep 9, 2020 at 3:31
  • \$\begingroup\$ The question about the clock frequency Fclk in the RC is because I'm having a kick-back voltage at the ADC input and creates peaks, so I thought about designing a bucket filter there. sorry about my grammar I'm not an English speaker. Thanks for your time \$\endgroup\$ Sep 9, 2020 at 3:31
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Generally, you need to limit the input signal to one-half the sample rate to avoid aliasing, based on the Nyquist Sampling Theorem.

More here: https://www.allaboutcircuits.com/technical-articles/nyquist-shannon-theorem-understanding-sampled-systems/

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  • \$\begingroup\$ And half the sampling rate is an ideal. Practically, unless you're interested in building complex brick-wall filters, keep it well below Fs/2. So, somewhere between 3 and 50 kHz : 6 or 10kHz would be my choice. And learn sampling theory as @hacktastical suggests. \$\endgroup\$ Sep 2, 2020 at 12:25
  • \$\begingroup\$ Over sampling is another, easier option if they actually need bandwidth to fs/2. Which they don’t in this case. \$\endgroup\$ Sep 2, 2020 at 17:15
  • \$\begingroup\$ The system could use a simple external filter to reject spurious noise (maybe a single-pole RC would be enough?), and internally some kind of low-poles FIR to further reject out-of-band signal. A 16KHz sample rate should be enough. \$\endgroup\$ Sep 2, 2020 at 17:41
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Aliasing can occur if the signal content after filtering is > LSB above fs/2.

Thus the amount of Nyquist filtering Fn, depends on the amount of noise and resolution. Often cutoff is around <=1/3 fs due to above conditions, with a high order filter.

If resolution was only 1 bit , Fn may be exactly fs/2.

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