I know this is a google before ask type question, but I didn't find the answer still on google. Then I went to library and refer some books but my changes were negative. I've searched more than 20 appendixes of books.

There are specific patents and there's no wiki page written on shallow diffusion.

Could you explain in simple what is called shallow diffusion? I mean in general.

--Thanks In Advance--

  • \$\begingroup\$ See answer below ... but the term diffusion is a hold over from earlier days and except for some old fabs is NOT used. In fact you can't make modern transistors with a diffusion step. \$\endgroup\$ – placeholder Dec 22 '12 at 18:24

In general, diffusion is one of the main ways in which doping changes are made in selected regions on the surface of a wafer. A fluid (gas or liquid) containing the desired dopant is flowed across the surface, which is masked appropriately. The time and the temperature of the wafer determine the depth of the diffusion.

Any particular fabrication "process" will typically involve several diffusion steps, with the deepest ones being done first, and the shallowest ones being done last. Other than that, there really isn't anything special about "shallow" diffusion.

  • \$\begingroup\$ I would disagree on the "anything special" but otherwise correct. \$\endgroup\$ – Sunnyskyguy EE75 Dec 22 '12 at 5:39
  • \$\begingroup\$ +1 voted for the answer and I accept this answer, this is clear. But I have seen by myself there are number of patents on this technology which are special cases. \$\endgroup\$ – Standard Sandun Dec 22 '12 at 8:27
  • \$\begingroup\$ sir there is no wiki page or a community wiki about shallow diffusion either, I think you guys could write it. \$\endgroup\$ – Standard Sandun Dec 22 '12 at 8:30

In modern CMOS processes there are NO diffusion steps. THey are called that as a historical hold over, but the process is one of implant and anneal. The reasons for this is many, but the main impact is that the junction and doping profile with depth can be controlled and you can go much deeper. In a true diffusion, you are stuck with a exponential tail distribution into the Si.

Diffusion MAY still be used in very old fabs that are producing discreet BJT's (even though they would do better with an implanter). But in CMOS there haven't been diffusion furnaces since teh switch to 200 mm wafers, 15 years or more ago.

With implant you can have ultra shallow junctions of a few nm's thick to 3u deep with a 1MeV + implanter.

  • \$\begingroup\$ I recall reading about ultra shallow diffusion of 28nm (high K) N & PMOS using spike & anneal diffusion suppresion then laser to create highly active ultra shallow jcn's for vertical and lateral. Where the Lateral dopant diffusion and activation had possibilities for improved Vth and Ron curve. Now 10 nm has been done in the lab. (But I'm no expert on it) \$\endgroup\$ – Sunnyskyguy EE75 Dec 22 '12 at 19:28
  • \$\begingroup\$ diffusion suppression = means that they DON'T want diffusion. There is always the fundamental physics in which you GET diffusion. But diffusion as a process is NOT used. All implants move during anneal because of diffusion, you'r confusing the usage of the term, which is confusingly used. "Highly active" ?- what does that mean. Annealing is also know as activation, which means that the implanted species have shared it's electronic orbitals with the Si and can now contribute acceptor or donors to the fermi level. But what you are describing is a research process paper, not production. \$\endgroup\$ – placeholder Dec 22 '12 at 19:37
  • \$\begingroup\$ true but relevant journal references documented the diffusion depth was ultra shallow using laser after RTA rather than just RTA \$\endgroup\$ – Sunnyskyguy EE75 Dec 22 '12 at 19:51
  • 1
    \$\begingroup\$ That has to do with heating profile to avoid too much diffusion. RTA does this as it "melts" just the surface, laser is one step above that in terms of depth of heat penetration. Sometimes used to bury photodiodes to prevent surface state pinning from the SI/SiO2 interface states. But nevertheless these are all diffusion SUPPRESSION steps (and here I talk about the physical process) NOT the semiconductor process. It's terminology that should have been suppressed a long time ago. \$\endgroup\$ – placeholder Dec 22 '12 at 19:58
  • \$\begingroup\$ gotcha now ok thks \$\endgroup\$ – Sunnyskyguy EE75 Dec 22 '12 at 20:17

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.