0
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im having problems figuring the problem for this The LinkDataRAM receives data and is tested, (we='0' AND re='1') condition is matched and the RAM should read from the LinkDataRAM For the values read im receiving, 0XX1X1, 01X1XX etc... What is the problem does anyone have any ideas? Is it something to do with multiple drivers, i dont have multiple drivers on the do1 and do2

library ieee;
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;

entity NodeRamMemory is
    port (
            clk : in std_logic;
            re : in std_logic;
            we: in std_logic;
            AbortNodeReadIn_RAM: in std_logic;
            addr1 : in std_logic_vector(2 downto 0);
            addr2 : in std_logic_vector(2 downto 0);
            addr3 : in std_logic_vector(2 downto 0);
            di : in std_logic_vector(5 downto 0);
            LinkDataRAM: in std_logic_vector(8 downto 0);
            do1 : out std_logic_vector(5 downto 0);
            do2 : out std_logic_vector(5 downto 0)
        );
end NodeRamMemory;


architecture syn of NodeRamMemory is

    type ram_type is array (7 downto 0) of std_logic_vector (5 downto 0);
    signal RAM : ram_type:= ("011111", "011111", "011110", "000110", "010100","010101","000101","000101");

begin
    process(LinkDataRAM) begin
       if(AbortNodeReadIn_RAM='1') then
            report "Node Ram Memory AbortNodeRead=1 received";
            if(we='1' AND re='1') then
              report "Node Ram Memory reads 1st Node from current Link and writes previous Link updated node value";
--              do1 <= RAM(conv_integer(addr1)); 
--              RAM(conv_integer(addr3)) <= di;
              
                elsif(we='0' AND re='1') then
                    report "Node Ram Memory reads 1st Node from current Link and no writes";
--                    do1 <= RAM(conv_integer(addr1)); 
                else
                    report "Node Ram Memory peforms no writing or reading";
            end if;
        elsif(AbortNodeReadIn_RAM='0') then
          report "Node Ram Memory AbortNodeRead=0 received";
          if(we='1' AND re='1') then
              report "Node Ram Memory reads 2 Nodes from current Link and writes previous Link updated node value";
--              do1 <= RAM(conv_integer(addr1)); 
--              do2 <= RAM(conv_integer(addr2)); 
--              RAM(conv_integer(addr3)) <= di;
              
                elsif(we='0' AND re='1') then
                    report "Node Ram Memory reads 2 Nodes from current Link and no writes";
                    do1 <= RAM(conv_integer(LinkDataRAM(8 downto 6))); 
                    do2 <= RAM(conv_integer(LinkDataRAM(2 downto 0)));
                else
                    report "Node Ram Memory peforms no writing or reading";
            end if;
        end if;
    end process;
end syn;
```
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  • \$\begingroup\$ IEEE Std 1076-2008 14.7.2 Drivers "Every signal assignment statement in a process statement defines a set of drivers for certain scalar signals. There is a single driver for a given scalar signal S in a process statement, provided that there is at least one signal assignment statement in that process statement and that the longest static prefix of the target signal of that signal assignment statement denotes S or denotes a composite signal of which S is a subelement." Your provided code has one process, so no multiple drivers. It's sensitivity list is also incorrect. What about elsewhere? \$\endgroup\$ – user8352 Sep 3 at 19:41
  • \$\begingroup\$ Why is the sensitivity list incorrect? The Data is received at LinkDataRAM, its been tested \$\endgroup\$ – Yanukova Yester Sep 3 at 20:28
  • \$\begingroup\$ 10.2 Wait statement lists the rules for constructing a sensitivity list, including process sensitivity lists. Every evaluated (read) signal should be in the list. \$\endgroup\$ – user8352 Sep 3 at 20:33
  • \$\begingroup\$ Seems like when i simulate just that component it works but doesnt work integrated \$\endgroup\$ – Yanukova Yester Sep 3 at 21:03
  • \$\begingroup\$ Im looking at the signals and doesnt seem to be any problems, what does X101X represent? \$\endgroup\$ – Yanukova Yester Sep 3 at 21:04

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