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I have two questions regarding routing power and ground.

  1. With respect to power, is it generally better to flood copper planes and have one via per pin/pad connecting directly to the plane under, or is it better to branch out from one via with a star topology? Pardon the sloppy layout, but see the below images where I have three bypass capacitors and a single via in the bottom picture compared to the individual vias for each pad connecting to a pour on the top one.

  2. Secondly, in regards to ground, I was viewing some board layouts based around RF chips that flooded all the empty spots with GND pours on top and bottom layers- what is the purpose/benefit of this? Free real estate for possible noise to couple onto?

One Via Per

Star Layout

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  • \$\begingroup\$ I'm interested in seeing a good answer to this as well. I can tell you that having smaller "loop" distances is better for EMI, so in theory having multiple pads for each bypass cap would create shorter loops versus having just one via at the bottom end of the trace feeding them. \$\endgroup\$ – JYelton Sep 3 '20 at 21:33
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    \$\begingroup\$ Straight to the plane. The plane has lower impedance than any trace so you want the current to complete as much of its journey as possible on the rather than some trace. \$\endgroup\$ – DKNguyen Sep 3 '20 at 21:42
  • \$\begingroup\$ Also, you should move your second question to a new question. \$\endgroup\$ – JYelton Sep 3 '20 at 21:42
  • \$\begingroup\$ @JYelton yes this seems to be the common wisdom. I was just thrown off by some professional designs I've been inspecting in PCB editors lately that seem to go against this. I guess the professionals know when to break the rules :) \$\endgroup\$ – jm567 Sep 4 '20 at 2:06
  • \$\begingroup\$ @jm567 Do you have examples of such designs? I'd like to see these exceptions too (sometimes they are also just older lower speed designs based on old design rules) \$\endgroup\$ – DKNguyen Sep 4 '20 at 4:43
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In my opinion, none of those 2 layouts are clean.

  1. Create a +5V_FUSE shape/polygon on top layer
  2. Connect the shape using one (or more vias, if you anticipate current to be >1A) on the north side of the northern capacitor to the L3 +5V_FUSE trace
  3. Connect the +5V_FUSE shape to all capacitors and pads, either by "capturing" them with the shape or running traces from the pad to the shape

This creates a neat power distribution to your chip, the capacitors acting a tanks for high-speed current transients with little to no parasitic to the chip's pads. Having the vias further away from the chip simply creates a shorted power path in your case.

I'm gonna answer your second question with another question. Do you have layer(s) with a lot of copper and others with only a small amount?

If you do, you should know that copper balance between layer is very important in high-volume production boards to prevent boards from warping during manufacturing heating/cooling phases. Unbalanced copper creates disparity in copper expansion and relaxation. Pouring a ground shape on all layers is recommended, accompanied by plenty of ground vias.

It also greatly helps with EMI reduction, as others mentioned. as long as you have plenty of ground vias all over your board and don't miss an isolated island of copper.

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  • \$\begingroup\$ Thanks for your take on this. The polygon on L1 + via to the power plane on L3 definitely makes more sense from a power distribution perspective than giving each individual pad/pin its own. However, when you have a bunch of disparate passive/active components clustered together, I suspect that they would need their own vias connected directly to the power plane in that case. I guess it is a matter of knowing when to apply what layout in that case. \$\endgroup\$ – jm567 Sep 4 '20 at 4:10
  • \$\begingroup\$ Not necessarily, prioritize the connections from the chip's pads to the decoupling caps, then worry about how the decoupling caps are connected to the main supply shape/trace. \$\endgroup\$ – eeintech Sep 4 '20 at 12:30
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  1. Star topology will prevent forming of loops that pick up unwanted signals.

Use large vias, with enough copper ring or a teardrop so that a misaligned via drill won't reduce the current path too much

If you have the room for multiple large vias, then it's preferred to stich to the plane from each point. You can also use multiple vias to reduce cumulative via resistance

  1. Copper GND planes provide low impedance path for current, reduce the effect of GND loops and provide EMC shielding.
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  • \$\begingroup\$ Thank you for your answer, Ralph. I know that GND planes provide low Z paths for current, but my question was in regards to the filling of all the unused area on signal layers with copper pour. For example, I am used to seeing GND only on layer 2 of 4 layer boards, but sometimes I see some designs fill whatever is left of layer 1 and 4 with GND after they are done routing signals. \$\endgroup\$ – jm567 Sep 4 '20 at 2:10
  • \$\begingroup\$ Old school designers would leave isolated copper areas, to have the manufacturing chemicals last longer. Some make a copper hatch to have the manufacturing chemicals have equal amount of dissolved copper, the SW might create the hatch automatically depending on other layout. Some may leave extra copper pours out so that that the view in CAD doesn't get cluttered, if they think one pour is enough. Or it might be easier to review GND paths if you only have one pour. \$\endgroup\$ – Ralph Sep 13 '20 at 11:58
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If you can control the distance between the power plane and ground plane that is ideal.

If you're talking about filling unused areas on signals planes I think that is a bad idea. Your board house will probably recommend this but it can cause unintended consequences. You can couple signals in the Z direction as well as the x,y.

Filling empty space with ground however can protect from signal and fields in the z direction.

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  • \$\begingroup\$ "If you're talking about filling unused areas on signals planes I think that is a bad idea" This is simply not true. It is recommended that all layers have the same copper coverage to prevent board to warp during manufacturing heating/cooling phases as unbalanced copper creates disparity in copper expansion and relaxation. Pouring a ground shape on all layers is recommended, accompanied by plenty of ground vias. \$\endgroup\$ – eeintech Sep 4 '20 at 2:46
  • \$\begingroup\$ Also, if you connect the copper fill to GND or power planes appropriately (usually GND though), the fill can act as pseudo planes for adjacent layers. There are some PCB designs with limited layers where this has been done which saved the design in EMI testing because the original design didn't have as enough dedicated plane layers. \$\endgroup\$ – DKNguyen Sep 4 '20 at 4:40

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