# What ADC requirements for 20 kHz to 10 MHz signal?

Currently, I am searching for an ADC which can read a sine wave signal with a maximum frequency of 10 MHz. I know that I have to choose an ADC of at least 20 MHz due to Nyquist theorem.

My signal of interest is between 20 kHz - 10 MHz.

Which ADC requirements should I take into consideration and why, for example: can't I use like an ADS4145 with 125 MSPS for reading signal from 20 kHz to 10 MHz?

• Requesting recommendations for parts are off-topic. Commented Sep 4, 2020 at 8:41
• With an ADC of 20MHz you will get two samples of 10MHz signal, if this is acceptable. Commented Sep 4, 2020 at 8:50
• As has a already been said, asking for recommendations is off topic. However, you could rewrite the question to ask about how you would choose a type of ADC based on your requirements. The answers to that would be interesting. Commented Sep 4, 2020 at 9:07
• "Some have said that an ADC can work to a certain minimum frequency without degrading of the ADC performance" - I've not heard this? It might be a good separate question to ask "is this true and if so why" Commented Sep 4, 2020 at 9:14
• I have changed something a bit now
– Kwok
Commented Sep 4, 2020 at 9:18

If you want to read a 10 MHz signal, then you'll need a sampling frequency somewhat above 20 Ms/s. A little bit above if you have a very good anti-alias filter, a lot above if you'd like an easier to design filter. I'd recommend nothing less than 30 Ms/s, and even then the filter will be quite challenging.

Very little degrades at low signal input frequencies. Most ADC parameters improve as the signal input frequency falls. The most demonstrable of these is the effect of phase jitter on the sampling clock. This converts a rapidly changing input voltage directly to noise.

At very low frequencies, we run into the rising 1/f noise of all semiconductor systems, though at 20 kHz an ADC should still be very quantisation noise limited rather than 1/f.

The best way to find an ADC for a specific purpose is to go to the usual manufacturers, Analog Devices, Texas, Maxim, and use their online parametric search tools. Or to find something from across all the manufacturers and have price and availabilty readily to hand, use the Mouser or Digikey parametric search tools.

There's no way any of us could make a useful recommendation, even if it weren't against the site rules (as recommendations for specific products would age very quickly as new parts come to market). For your particular application you'd also need to factor in considerations like the data interface (serial, parallel, LVDS, CMOS, JESD, it matters at 30 Ms/s 16 bits), power consumption, cost, package, single ended or diff inputs, on board reference, and of course noise, spurious, drift, accuracy specifications.

Happy searching.

You've mentioned the ADS4145 ADC at 125 Ms/s. That's a fine device. It will read 10 MHz and 20 kHz quite happily. There are two things you can do if you only want to read to 10 MHz. One is to reduce the clock rate to the ADC, meaning there's less output data to handle. The other is to decimate the output data digitally, meaning you'll get a small improvement in noise through oversampling, and a much easier to design anti alias filter. If you're happy with the tiny device, the DDR LVDS output, and the price, there's no reason not to use it.

• Thank you for your response. What do you mean with 'though at 20 kHz an ADC should still be very quantisation noise limited rather than 1/f.'?
– Kwok
Commented Sep 4, 2020 at 9:23
• @Kwok for 'typical' systems, you'll find that the dominant noise source will be a flat SNR, rather than a rising 1/f noise, at 20 kHz signal, when read with an ADC. Commented Sep 4, 2020 at 10:05

Following up on the excellent guidelines from Neil_UK, I offer these additional thoughts:

• the phasenoise (the sampling jitter) that limits the high_slewrate noise floor, may depend on external circuits and PCB routing.

• the digital interface may limit your ENOB (your noise floor), because external clocking of ANY interface will dump charges into the ADC silicon, and that charge will explore all possible paths to return back to the originating clock driver. And massively parallel data movements out of the ADC will require lots of charge supplied FROM within the ADC, causing 0.5 volt movment of the ADC VDD and GND pins. If you want the cleanest ADC performance (quietest on_chip analog comparator binary_search decisions), then have NO DATA MOVEMENTS during sample/convert tasks. In other words, you need a 3_phase ADC: sample, convert, move_data (repeat)

• from what I've learned from chatting with design_teams of over_sampling ADCs, the 1/F noise (from surface flaws in the silicon crystal that store/unload/store single electrons) is merely another contributor to the overall noise added to the binary_search decisions of the analog comparator; thus even at 1Hertz or 10 Hertz or 100Hertz (or 20,000 Hertz conversion rates), the analog decisions will have the same uncertainty (code spread) as at 10MHz.