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I have a CD4017 counter configured so that any of its outputs can be connected to the reset pin. I also have a manual reset button connected to the reset pin, and this switch is buffered by a Schmitt trigger.

The problem is that the Schmitt trigger holds the reset pin low and any CD4017 output connected to reset pin is not able to drive it high and trigger the reset.

I tried adding a resistor in series with the Schmitt trigger output, but this only reverses the problem... the CD4017 output overpowers the reset pulse from the Schmitt trigger.

How would you suggest solving this problem?

Enter image description here

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  • \$\begingroup\$ What is the Schmitt trigger in? From the CD4000 series? CD4106, CD4584, or CD40106? \$\endgroup\$ – Peter Mortensen Sep 5 '20 at 18:53
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You can do this. You don't really need the ST gate on an asynchronous RESET input, and if you did, you'd need more parts to make it work properly.

schematic

simulate this circuit – Schematic created using CircuitLab

Edit (retaining the gate):

schematic

simulate this circuit

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  • \$\begingroup\$ I do need the st gate, for clarity I simplified the circuit but in reality it is important, what suggestions do have for keeping the st in the circuit? \$\endgroup\$ – Jay Sep 4 '20 at 15:36
  • \$\begingroup\$ Add a 1N4148 diode from the gate output to the reset input and retain the 10K resistor as above. \$\endgroup\$ – Spehro Pefhany Sep 4 '20 at 15:39
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You want reset to be triggered when the schmitt trigger is high OR the CD4017 output is high.

This is the classic use case for an OR gate.

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  • \$\begingroup\$ good suggestion, this is how I should have done it in the first place. \$\endgroup\$ – Jay Sep 4 '20 at 15:49
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You've rediscovered an important principle - standard logic outputs cannot be connected together. If they are set to different values (one 0, the other 1) they will pull their common connection to an indeterminate value. You may damage one or both gates due to excessive current. Any inputs fed from their common connection will not see a clean logic level and may misfunction. (Instead of seeing a clean '0' or '1' voltage they can see something in-between.)

The standard solution is that posted by Justin. Each output you wish to combine needs to be taken to a separate input on a suitable logic gate (here an OR gate) that combines the signals and provides a single output to drive the next stage (your reset input).

You can, as variously suggested, build your own diode OR gate but the normal practice is to use a logic gate of the logic family you are already using, which retains the speed and drive ability of that family.

Another method used to combine outputs, not applicable here, is the wired-OR connection. This uses a pull-up resistor, connected to the +ve supply line, and gates with special outputs known as open-drain (MOS) or open-collector (bipolar transistor).

Speaking of pull-up resistors, your manual reset circuit would benefit from a pull-down resistor to ground between the switch and the Schmitt trigger input. Whilst a CMOS Schmitt trigger input apparently doesn't have to have one it is still good practice to provide one and it is required for non-Schmitt CMOS inputs, which should never be left to float.

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Try these simple additions in red: -

enter image description here

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Two things. First, you show no passive components around the triangle symbol, what I assume is the Schmitt trigger component you mentioned. Without some timing components, a Schmitt trigger gate will do very little by itself to debounce a switch. There are many sites with circuits and descriptions for switch debouncing.

Second, there is no Schmitt trigger OR gate (that I know of). You can add a 2-input OR gate after your debounce circuit, and tie in the output from the 4017. Or, you can create one with two diodes and a resistor. This is called a diode-OR circuit.

Edit: Andy posted a diode-OR circuit while I was typing.

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