can connecting a tristate buffer output to 0 or 1 make problem?

Question

in this circuit the control line is connected to GND so the output is Z. is there any problem to connect the output line to 1 or 0? if the control line turns to 1, what happen to the circuit? what is your answer about the second circuit which is made with transistor?

Answer 1

The GND symbol represents metal plates buried in the earth. It should always be drawn pointing down. You can't earth something in the sky.

You need to state in your question whether the buffer is enabled when the enable input is 0 or 1.

Is there any problem to connect the output line to 1 or 0?

There is no problem if the output is in tristate because it is floating.

If the output is not in tristate then it should not be connected to a line that is being pulled high or low by another device. If you do then high currents will result and the logic level will be somewhere in between 0 and 1 so it will be undefined. There should only be one device putting data out on the line.

What is your answer about the second circuit which is made with transistor?

There is not enough detail.

Answer 2

Silicon transistors can be damaged/destroyed in just one microsecond, because of the tiny size of the implanted silicon regions and the very high current_conductivity possible.

At 100 uA/Volt^2 for Nchannel devices in 0.25 micron, a 25/0.25 device with 5 volts on the gate (and Vthrehold of 0.7 volts), produce

• Idrain = K/2 * W/L * (Vgs - Vt)^2 if in fet_strurated region, and not velocity _limited.

which produces

• Idrain = 100uA/2 * 25/0.25 * (5 - 0.7)^2

• Idrain = 50uA * 100 * 4.3^2 = 5 milliAmps * 19.5 ~~ 100 milliAmps

in a region of size (0.5 micron for souce-drain stipes, 0.25micron for minimum lnght (mazimum conductivity) gates) 25 micron by (0.5 +0.25 + 0.5 + 0.5 on each side) or about 25 by2.25, which will be laidout on silicon as more squarish, as 10 by 6 micron or so.

The key feature, in heating, is the DEPTH. Regardless of the surface area, the implants for source and drain and wells will be about 1 micron (or less) for 0.25 micron.

The thermal timeconstant for 1 micron depth is 11.4 nanoseconds.

The specific heat for silicon is 1.6 picoJoules per cubic micron per degree K.

We may be Velocity_limited in the drain current, which serves to prevent the square_Of_gate_voltage remaining valid.

But let us assume there is no Velocity_Limitation.

The power dissipation, given 5 volts on gate and 5 volts on drain is

100 milliAmps * 5 volts == 500milliWatts , thus 0.5 joule per second.

This (we'll assume) is spread over th esurface area of th eFT, which we computed/estimated as 60 microns^2 (with sharing of source regions and of drain regions, this could be 50 or 40 micron^2, so assume 50 microns^2)

The energy per square micron is 500mW/50 square micorns = 10 milliWatss per square micron.

How fast will this heat up?

Rgions of the FET in th emiddle, surrounded by other similarly heating resiongs, can only dump heat UNDERNEATH. That heat flow can be estimated as a triangular heat/temperature profile. And we can easily work with triangles, the area being 1/2 of that of a rectangle.

In 11.4 nanoseconds, the heat will (mostly) remain in the top 1 micron.

How hot will that become in 11.4 nanoseconds?

5 milliWatts * 11 nanoseconds = 55 picoJoules.

And heat capacity of 1.6pJ ===> 55/1.6 = 33 degree C temperature rise. In 11 nanoseconds.