# Assigning to a parameterized 2d Verilog array

I have a Verilog array defined as :

logic [ 0 : num_elements - 1 ] [ element_width - 1 ] some_array ;


I want to assign every array element with a vector that is all ones: "11...1". I tried this but I get an error:

some_array <= { num_elements { element_width { 1'b1 } } } ;


What's the correct syntax ?

To assign unpacked 2d array in SystemVerilog with a single line:

some_array <= '{ default: '1 };


Verilog cannot be done in a single line. It must use a for-loop:

for ( i = 0; i < num_elements; i = i +1)
some_array[i] <= {element_width{1'b1}};

• Suppose: num_elements = 4 element_width = 8 Making it more complicated I want each element to get "0xFA" So now - my ONLY option is to use the for-loop approach ? There's no way to do it in a single line like in VHDL ? some_array <= ( others => ( others => x"FA" ) ) ; Sep 7, 2020 at 9:02
• @shaiko the SystemVerilog '{default: } approach will still work. Refer to the SystemVerilog LRM
– Greg
Sep 7, 2020 at 17:30
• It'll work for packed as well as unpacked array ? Sep 7, 2020 at 17:45

Since some_array is all packed, you can do

some_array <= '1;

• What if it was unpacked ? Sep 6, 2020 at 20:10
• I'm looking for a syntax to assign each array element individually...similar to what I wrote in my example. Sep 6, 2020 at 20:34
• In your example, each element is a single bit. You might want to check out the default: clause of an array assignment pattern Sep 6, 2020 at 22:55