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This picture is shown on Wikipedia.

enter image description here

From my understanding of shoot-through, I think this circuit will shoot-through every cycle of pulse and destroy itself.

  1. Will it shoot through or are there any hidden elements to prevent it?
  2. Can I make discrete CMOS logic based on this circuit? Or which circuit will work?
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    \$\begingroup\$ If Vgs(th) is about Vdd/2, there will be no shootthrough. Guaranteeing this with discretes is your problem... \$\endgroup\$ Sep 7, 2020 at 21:16
  • \$\begingroup\$ The CD4069 datasheet shows its fairly low typical shoot-through current. But I cannot add the image from the datasheet. A 74HC shoot through current is much higher and causes destruction if the switching speed is too slow. \$\endgroup\$
    – Audioguru
    Sep 7, 2020 at 21:39
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    \$\begingroup\$ Strategies exist to mitigate it to the point where it typically costs power not damage, but there is shoot through in many CMOS structures; it's why you don't want an input sitting at an intermediate voltage where both upper and lower FETs are a little bit on. \$\endgroup\$ Sep 7, 2020 at 22:01
  • \$\begingroup\$ I imagine a difference in capacitance between the two mosfet gates can create a short delay avoiding shoot through. \$\endgroup\$
    – Fredled
    Sep 7, 2020 at 23:35

3 Answers 3

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Yes, there is (some) shoot through, but it is not particularly significant.

  1. In normal CMOS circuitry, the input signal transition is quite fast. Therefore the time during which both devices are (partially) on is quite small.
  2. When there is shoot through, the total shoot through current is still less than the peak current the devices handle (because VDD is partitioned between both devices).
  3. In CMOS circuits the current wasted by shoot through is usually smaller than that wasted by charging (or discharging) the load capacitances.
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  • \$\begingroup\$ Good answer and succinctly summarizes the major issues involved. \$\endgroup\$
    – SteveSh
    Jun 21, 2021 at 0:31
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I've guided design teams, to produce control logic with minimal upset to VDD caused by logic transitions. The key

  • use long channel CMOS --- may be 5nanosecond Tpd instead of 50pS Tpd

  • operate the CMOS gates/FFs at reduced VDD (not 5 volts)

  • have an RC filter between global VDD and the LOGIC VDD: 100 pf and 100 ohms

  • have controlled_slew output driver(s)

Result? passed FCC emissions on first_test.

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  • \$\begingroup\$ then I can't create this circuit with narmal mosfet? \$\endgroup\$
    – M lab
    Sep 8, 2020 at 5:46
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Here is an image of fairly enter image description herelow shoot-through current in the datasheet of a CD4069:

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  • \$\begingroup\$ So, how these happen? I think if I grab some mosfet and rebuild this circuit it certainly destroy itself. \$\endgroup\$
    – M lab
    Sep 8, 2020 at 5:44

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