# Re: decoupling capacitor design calculation

I was searching a bit about the decoupling capacitors. All I was able to find is electrolytic capacitor is used for low frequency noise filtering and ceramic capacitors are used for high frequency noise filtering. I could not find any formula to determine the values for the same. Can someone please guide me on the approach to be followed and formula to determine the values?

PS: I am aware that multiple electrolytic caps are used because of the ESR and the ESL of the capacitor.

• $$I = C\dfrac{dv}{dt} \hspace{1cm} \text{is a good starting place}$$ Sep 8 '20 at 15:20
• A good way to think about the problem is that you are building an LC lowpass filter that filters out noise coming from the IC's supply pins and that shouldn't go to the power supply. The only thing that deviates from that model is that you really want to filter the highest frequencies as close to the source as possible. For a flat frequency response (i.e. good suppression of all frequencies higher than the power supply's switching frequency), you need to combine multiple filter stages. Sep 8 '20 at 15:49
• I have never seen anyone try to use a formula to figure out decoupling. A rule of thumb is one 0.1uF ceramic cap per power pin (placed close to the power pin). Plus at least one bulk capacitance on the PCB. Bulk capacitance could be 1uF, or 100uF, or even more depending on what the board does. Sep 8 '20 at 17:40 but a capacitor has a series resistance (ESR), that means we can not get back all the Energy we want back out of the capacitor and we will suffer a additional voltage drop.

So lets allow 0,05V drop at the ESR. This means our capacitor only is allowed to drop by 0,05V.

we recalculate and now we need 800uF not 200uF !

Also we know our µC will draw 1W of power with a 0,1V drop... this is - assume a 3,3VµC 1W/(3,3V-0,1V)=0,3125A of current. with an allowed drop of 0,05V at the ESR and 0,3125A current the ESR must be equal or lower than 0,05V/0,3125A = 500mOhm

So for our scenario you need a 800uF capacitor with a ESR < 500mOhm to supply 1W for a µC running at 10MHz for 10clocks with a voltage drop of max. 0,1V

OK, lets simulate it

first a weak source which will drop at our load condition without the capacitor:  We see a drop by ~0,2V. Thats to much. so we connect our capacitor  and now we see what we expect. the voltage drop is reduced, current flows out of our capacitor (neg. direction)

• Nice answer. A question I have is which voltage drop are you referring to? I'm assuming, since the capacitor is in parallel with the IC device, that the voltage drop you're referring to would be across the series resistance and inductance (i.e. impedance) of the copper trace between the supply and IC device. Is this correct? So, for instance, if the IC device draws more current the voltage drop across the trace becpmes higher and the voltage at the pin of the IC would be lower. The capacitor is mean to correct for this? Is this correct? Sep 8 '20 at 18:52
• @mrbean when you have a 3,3V IC, the data-sheet will state, it will operate at e.g. 3,3V +-10%. this minus 10% is the max. allowed voltage drop. if you do not buffer this, logic errors might occur. The trace impedance is a problem which gets larger with higher frequencies - yes. This is why you want the buffer capacitors near the sink and or a very low impedance supply plane. Also you can combine capacitors of different sizes which have different frequency dependent resistance and different ESR Sep 8 '20 at 18:59
• @mrbean of course, if the data sheet states -10%, you design to buffer -15 or even -20%. first to cover parasitic effects, plus there is aging of the components. Sep 8 '20 at 19:05