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I built a ring oscillator out of discrete logic gates as in the following schematic:

ring oscillator

It consists of 6 inverters/NOT gate (SN74LVC1G04@U12-17) and one NAND gate (SN74LVC1G00@U11) so the circuit can be reset.

schmitt-trigger

In addition to that, I added a Schmitt-trigger (SN74LVC1G17@U19) to clean the output and a button to reset the circuit.

At first glance, the circuit seems to work. Here is the output of CHAIN1 (yellow) and CHAIN1_OUT (blue, output of Schmitt-trigger) on my oscilloscope: glitch-free waveform

However, this circuit sometimes glitches as captured below: glitch waveform

These glitches appear at irregular interval (~every 30-100 cycles). Where do these glitches come from and how can these be fixed?

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    \$\begingroup\$ One has to wonder if they are coming from something not intended to be and not depicted as part of the experiment. Two obvious concerns however are the lack of bypass capacitors on the logic power supplies, and the presence of the LEDs. Unless someone convinced you those LEDs are a critical part of the circuit (which they don't seem to be), you may want to remove them, as their non-linear knee complicates the output slew substantially. The interaction with the lack of bypass capacitors could be particularly interesting. \$\endgroup\$
    – Chris Stratton
    Commented Sep 9, 2020 at 16:09
  • \$\begingroup\$ What exactly is the instrument used to capture this? The lack of metadata on the plot makes it look like some sort of PC-based quasi-scope or data output from a conventional one. Is the instrument truly of professional grade and actually known to be bug-free? \$\endgroup\$
    – Chris Stratton
    Commented Sep 9, 2020 at 16:11
  • \$\begingroup\$ My wlid guess: your oscilloscope probe slipped. \$\endgroup\$
    – user20574
    Commented Sep 9, 2020 at 17:38

1 Answer 1

Reset to default
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This is a guess. Your circuit has unexpected feedback route via the power supply rails. You have not inserted proper decoupling capacitors, there's substantial noise in the operating voltage pins of the ICs due the high current peaks which can be expected due your slowly changing logic input signals.

BTW. for reliable results you should use components within their specified operating areas. Logic gates shouldn't be used with slow input signals. They can behave unpredictably even without super noisy operating voltage when the input is in the undefined range. I do not claim nobody has got their out-of-specs circuits working, for ex. I have succesfully used CMOS inverter as a linear amp but I've been lucky.

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