# Understanding "Verilog default:’1"

I have a few questions about what this code does and how it works:

x <= '{default:'1} ;

1. What is the purpose of the "default" keyword ?
2. What is the purpose of the inner single quote apostrophe before the 1 in this case ?
3. What is the purpose of the inner single quote apostrophe before the { in this case ?
• Stackoverflow has a question on this.
– user103380
Sep 9, 2020 at 19:59
• I've read the question on Stackoverflow before posting this one. I'm not asking the same thing. Sep 9, 2020 at 22:40

The inner single quote before the 1 is a numeric literal fill. The '0, '1, 'z, and 'x literals will be extended to fill the width of whatever context they are used in.

The outer single quote before the { means that this is an assignment pattern to an array or struct. Assignment patterns require a value for every element of the array or struct, which can be positionally ordered or matched by name/index. When matched by name/index, the default: serves as a match to any unspecified element.

This is all explained in section 10.9 Assignment patterns in the IEEE 1800-2017 SystemVerilog LRM

• In fact your answer states the same as mine, except you use more formal terms. But it's in no way more correct. Sep 10, 2020 at 7:14

As far as I know:

• its SystemVerilog
• '{} defines a (unnamed) struct
• default:'1 , as the default width is 32bit, is 32x '1' as constant

(if not correct, please correct me)

• This is completely incorrect (other that yes, this is SystemVerilog as it was so tagged) Sep 9, 2020 at 21:45
• dave_59, so what's the correct answer ? Sep 9, 2020 at 22:05
• @schnedan - Since we don't know what x is, we don't know what it defines. And there is no default width for '1 in this context. We need to know x's width. Sep 23, 2020 at 8:23