My design is deployed around a particular tile in the FPGA, mainly because of a gigabit transceiver that is located there.

However one of the clocks needed for the gigabit transceiver has to come from a pin that is on the far end of the die.The propagation delay of that clock causes timing errors.

What would be a way to reduce the propagation delay of a clock in such an arrangement?

  • \$\begingroup\$ If' you're using a gigabit transceiver, you should be using it in a way that is not going to be troubled by cross-chip propagation delays. I strongly recommend reviewing exactly what you're trying to do at the system level, and whether you've chosen the right tools for the job, or using those tools in they way they were intended to be used. Gbit transceivers are intended to work with data frames of such size that fine timing is not required to get data in and out, and the serial itself is async and self-timed. \$\endgroup\$ – Neil_UK Sep 10 '20 at 10:26
  • \$\begingroup\$ @Neil_UK I am simply trying to utilize the example design generated by the IP (of Xilinx). My intention is to be not far from the already deployed methodology of the example.The GT requires 2 clocks one reference and one free-running, when you say fine timing is not required you mean that the clocks is not necessary to come from a IO? \$\endgroup\$ – Rizias Sep 10 '20 at 10:32
  • \$\begingroup\$ @Rizias usually, FPGA vendors design their transceivers such that a clock is either part of what it can output, or there's a clockable pin close enough. \$\endgroup\$ – Marcus Müller Sep 10 '20 at 10:40

Two key concepts:

  • FPGAs in general (and Xilinx FPGAs in particular) have clock distribution networks that are designed to deliver clocks with low skew across the entire chip.
  • A PLL (or DCM) can be used as a zero-delay clock buffer.

Combining these concepts gets your clock across the chip with essentially zero delay.


simulate this circuit – Schematic created using CircuitLab

The PLL adds enough delay so that the total delay through it and the clock distribution network is exactly one clock period. Since that means there is essentially zero delay between the PLL inputs, and there is zero delay among the loads of the clock tree, the transceiver gets a clock that has essentially zero delay from the input pad on the other side of the chip.


Pretty much the only (and the usual) solution is to add enough delay to the outputs that you care about, so to compensate for the propagation delay.

  • \$\begingroup\$ Thank you very much for your reply.In Xilinx's terms then we talk about "set_input_delay" ? \$\endgroup\$ – Rizias Sep 10 '20 at 10:19
  • \$\begingroup\$ @Rizias doesn't set_input_delay just tell the synthesizer when your signals arrive? They still have to actually arrive at the time you told it they would. \$\endgroup\$ – user253751 Sep 10 '20 at 10:48

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