I have a design with multiple inputs and outputs that should have different bit rates, configurable at runtime. Since there are more I/Os than PLLs, I need to share some PLLs, e.g.:
- port 1: 1 Mbps
- port 2: 1 Mbps
- port 3: 15 Mbps
Ideally, I'd like to route an 1 MHz clock to the output stage of ports 1 and 2, and a 15 MHz clock to the output stage of port 3. If port 2 gets reconfigured to use 15 MHz as well, the clock routing should be changed so port 2 switches to the other clock network. If instead port 3 is reconfigured to 20 MHz, the PLL driving that clock network should be reconfigured at runtime.
Is that possible with normal FPGA architectures to make clock routing elements visible to VHDL, or should I just go with generating a clock that has a high chance of being a multiple of any baud rates I want to support, and dividing it locally on each port with enables?