It's my first time working with 7408 chips and I'm facing some issues. The chip I'm using is SN74LS08N.

The working principles of AND-gate chips are as follow. 7408 IC

I give my chip 5V supply at pin 14 and connect pin 7 to ground. According to the truth table, without connecting anything, the input pins are at LOW and the output pins should be also LOW. But the output pins are giving out HIGH voltages. No matter which combination I connect it is always giving out HIGH.

I also tried connecting the outputs to ground and now the outputs are always at LOW, even with two HIGH inputs.

Is my chip broken or is there something I'm doing wrong?

  • 3
    \$\begingroup\$ No. Without connecting anything the inputs are UNDEFINED and in bipolar 74 series, drift high. Your chip is fine, but don't leave inputs floating. \$\endgroup\$
    – user16324
    Sep 10, 2020 at 11:31
  • 3
    \$\begingroup\$ Possible duplicate of AND gate output when inputs are open \$\endgroup\$
    – CL.
    Sep 10, 2020 at 11:31
  • \$\begingroup\$ @BrianDrummond I have also tried with HIGH inputs that come from 5 V line and LOW inputs that come from GND but they also give me HIGH outputs. \$\endgroup\$ Sep 10, 2020 at 11:38
  • 2
    \$\begingroup\$ Well if you connected the outputs to GND you may have destroyed it. \$\endgroup\$
    – user16324
    Sep 10, 2020 at 11:41

2 Answers 2


The assumption that connecting nothing means logic 0 is wrong. That is not how LS series chips work, as they consider no connection as logic 1 input. Also, leaving inputs unconnected can be considered bad practice anyway, so they should not be left unconnected to begin with.

And, you are also not supposed to short the chip output to ground, it is also incorrect use of the logic chip and can damage it.

Chips will only provide valid outputs with valid inputs.


Although it is not recommended to leave inputs open, an open TTL input is a high (sorta) in the sense that no current is flowing in the input

Here is the schematic of the 74LS00 2 input NAND gate:

74LS00 Schematic


As you can see, with no active input, the input is pulled high internally so it appears to be a high.

Any local noise could change that effective state, though.

  • \$\begingroup\$ You find the shematic of the gate so fast! You are awesom! \$\endgroup\$
    – Arseniy
    Sep 10, 2020 at 12:21

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