In this day and age we can just use the memory IP provided to us by the FPGA vendor be it a soft IP or hard IP. This makes it almost trivial to communicate with high speed memory devices like DDR2 and DDR3 RAMs from the FPGA side. The PCB layout is still a massive challenge though and there is no doubt about this at all.
Many years ago I read that once upon a time, the engineers had to design a memory controller for high speed RAMs themself for an FPGA being used in their design. I am not sure how often this happened. I remember reading that at that time, the most difficult part of the memory controller design was the PHY.
From memory I can remember that it gave a reason as well. The reason it gave is that the PHY required very precise control of propagation delays and this required some sort of novel idea to be achieved in FPGA that has this issue with a nondeterministic propagation delay between different cells every time we compile the design.
Is this true? If this is true, how was this problem solved? I have never found details of this anywhere but I am curious to know what special steps engineers took to solve such a problem. It seems that they had to specify very tight timing constraints for specific paths and let the fitter do the rest, but if all it took was some SDC constraints, that does not appear too difficult to me in theory.