How do I build an RC-base negative edge detector, that makes a low pulse on a falling edge?

Question

I keep coming back here searching for an RC-based negative edge detector for TTL levels, that generates a negative pulse on a falling edge. The only place I find this solution is a certain spot in a certain video by Ben Eater. But I keep forgetting it and there is no clear entry on this site about it, and I'm tired to go back to a video to jog my memory.

Note: I have already answered the question with the only way I know. But it has problems, and therefore I am not accepting my own answer, but the answer that has fewer issues, and is simpler than mine.

Answer 1

How about this simple circuit?

^{simulate this circuit – Schematic created using CircuitLab}

Where \$RC\$ time constant should be much lower than the input impulse duration.

Or use a NAND monostable gen

Monostable out of NAND gates

Answer 2

Riffing off the clock doubler (with an XOR gate) in, I think it was Peter Alfke's classic "Six Easy Pieces", you can generate short pulses off a single edge.

^{simulate this circuit – Schematic created using CircuitLab}

Shortly after the negative edge on the input, both inputs to the OR gate are low, until the inverter output goes high, and with a time constant = RC, so does the delayed input to the OR gate. If the logic level differentiating '0' and '1' is Vcc/2 the delay will be the half-life ofthe R-C circuit or about 0.7*RC, or 70ns with the values given, but in practice it will depend on the logic family.

Answer 3

The only place where I find this answer documented is in Ben Eater's video "Using an EEPROM to replace combinational logic" at this particular time linked here.

This needs to be shown in schematics. I happen to want his ~600ns pulse width in my application too, so I use his exact values for R6 = 680 ohm and C3 = 1 nF for a 680 ns pulse. And the R5 resistor is there to re-charge the capacitor. Please excuse that I am showing the schematics in a certain application of a ramp generator that I'm building. Falling edge of a counter is supposed to reset the ramp. But the circuit in question here is all aroun R5, R6, C3, and D1, along with the rectangle wave from V2. The gate of M1 is simply the output pulse I want.

I added D1 to Ben Eater's circuit to chop off the +10V pulse on the rising edge. It may not matter with my MOSFET application, but it probably does matter on a TTL input pin to run it out of spec.

Here is the detail view of the negative pulse, and don't worry about the red trace, which is the charging of C1.

Here is the trace showing the positive edge pulse too, chopped off by D1. The problem of this is that it works with the switch application that Ben Eater uses, but it might not work driven directly by a TTL device since the momentary current it needs to sink to discharge C3 (a whopping full ampere) is not possible with a TTL device.

So I wonder if I need to deploy another MOSFET, an n-channel to do the discharging.

and this seems to work. Not sure if it is the simplest solution, but it is doable.

without that n-MOSFET M2 the resistance of the pulse generator would not be enough to generate that negative pulse.