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a) Should I learn VHDL or Verilog? Is one excel in some area while the other better fit another area?

For simple "glue logic", says, 5 to 30 TTL chips equivalant, which is better?

b) First learning exercise is to implement a stop-watch counter. One I/O pin to start count. One pin to stop. One pin to clear. Same as MCU TIMER CAPTURE, but higher count frequency. Source of example program appreciated.

c) Second exercise is to PARALLEL LOAD counter into shift register. Send data to MCU, using software control CLOCK and DATA pins (or MCU hardware SPI), to reduce pin as in parallel out. Example appreciated.

d) Altera WIZARD can create parameterized counter. Will WIZARD better than VHDL/Verilog in getting highest possible counting frequency to around 200MHz to 350MHz? Is FLOOR PLANNING easy to learn? Will Wizard/VHDL best suit FLOOR PLANNING?

e) I intent to buy Altera EPM570 development board. Is it suitable for above application?

f) Which brand/model consumer/industrial grade IC (CPLD or FPGA) has highest counting frequency (200 to 600MHz) for simple counter with START, STOP, CLEAR pins?

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closed as not a real question by clabacchio Dec 25 '12 at 18:32

It's difficult to tell what is being asked here. This question is ambiguous, vague, incomplete, overly broad, or rhetorical and cannot be reasonably answered in its current form. For help clarifying this question so that it can be reopened, visit the help center. If this question can be reworded to fit the rules in the help center, please edit the question.

  • \$\begingroup\$ Although a potentially good question, this one needs a radical improvement, and therefore I've closed it. You should focus on one problem (no multiple questions) and make a clear question. Also it's not very constructive to ask for specific code, unless it's used to explain a concept. \$\endgroup\$ – clabacchio Dec 25 '12 at 18:35
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(a) My own preference is (strongly) for VHDL - in many ways, with VHDL, you know where you are, more accurately, than in Verilog. I described some of these ways in this answer and another answer there gave this useful link.

VHDL is said to be more verbose, but I find that its HLL features let me create hardware at a higher level, and that offsets the verbosity and makes my designs smaller and easier to understand.

That being said, if C is your favourite software language, you might well prefer Verilog, and either language will certainly handle your task. So it comes down to preference.

Either way, learn the simulator, and get into the habit of writing a self-checking testbench alongside your design units. Progress may initially seem a little slower, but definitely smoother.

(b) Example counter...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

entity count is
    Port ( clk   : in  STD_LOGIC;
            -- reset : in  STD_LOGIC;
           start : in  STD_LOGIC;
           stop  : in  STD_LOGIC;
           clear : in  STD_LOGIC;
           data  : out UNSIGNED (7 downto 0));
end count;

architecture Behavioral of count is

type State_Type is (Idle, Run);

begin

Counter : process(Clk) is
variable Count : UNSIGNED (7 downto 0);
variable State : State_Type := Idle;
begin
   if rising_edge(Clk) then
       -- if reset = '1' then ... setup power-up state here
       if clear = '1' then
           Count := (others => '0');
       elsif State = Run then 
           Count := Count + 1;
       end if;
       if start = '1' then
           State := Run;    -- variable assignment
       elsif stop = '1' then
           State := Idle;
       end if;         
       data <= Count;   -- signal assignment
    end if;
end process Counter;

end Behavioral;

And a testbench. Note that it verifies the outputs and reports errors, rather than leaving you to stare at waveforms. That's what I meant by self-checking. To be even stricter I could set severity Failure and have it abort at the first error it finds!

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

  ENTITY test IS
  END test;

  ARCHITECTURE behavior OF test IS 
  signal testclk  : STD_LOGIC := '1';
  signal start    : STD_LOGIC := '0';
  signal stop     : STD_LOGIC := '0';
  signal clear    : STD_LOGIC := '0';
  signal test_out : UNSIGNED (7 downto 0);

  constant Tcy : time := 10 ns;

  BEGIN

  UUT : entity work.count
    Port map ( clk => testclk,
             start => start,
             stop  => stop,
             clear => clear,
             data  => test_out );

  --  Test Bench Statements

  testclk <= not testclk after Tcy/2 ;  -- 100MHz

     tb : PROCESS
     BEGIN
        wait for Tcy/2; 
        clear <= '1';
        stop  <= '1';
        wait for Tcy; 
        clear <= '0';
        stop  <= '0';         
        -- check counter is stopped and clear
        wait for Tcy;
        assert test_out = 0 report "Counter is not clear" severity error;
        wait for 5*Tcy;           
        assert test_out = 0 report "Counter is not stopped" severity error;
        start  <= '1';
        wait for Tcy; 
        start  <= '0';  
        -- check counter can count!  
        wait for 5 * Tcy;         
        assert test_out = 5 report "Counter is not counting correctly" severity error;
        report "Counter has counted to " 
                  & natural'image(to_integer(test_out)) severity note;
        wait for 5 * Tcy;   
        report "Tests complete : not a failure!" severity failure;
     END PROCESS tb;
  END;

(c) left as an exercise...

(d) For simple things like counters, my view is that vendor IP is just a good way to lock you into a vendor. Straight VHDL can be synthesised very efficiently and compiled for any vendor. When you get up to DDR2 memory controllers and CPUs, it's a different matter.

d2) Floorplanning may buy you 30% more speed if you are willing to take the time to learn it and fiddle with the placement of the design. My experience here is Xilinx; for Altera, YMMV.

e) How about a link to the board so we can comment?

f) Latest generation. If simple speed matters, choose the smallest (expensive) Virtex-6 over a large (cheap) Spartan-6 though I guess even the S6 can count at 300+ MHz. I can't comment on Altera products.

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  • \$\begingroup\$ A lot of engineers use Verilog and there are many that prefer VHDL. You likely need to learn both if doing this for a living. However, I learnt VHDL from this free book which I found very easy to read. VHDL fits which my obsessive nature a bit more! That website sells a little devboard with a paper version of the book for $79 which is nice (I haven't used this board though!) \$\endgroup\$ – carveone Dec 24 '12 at 13:16
  • \$\begingroup\$ Hi Brian, a) What is "habit of writing a self-checking testbench"? I guess you refer to, says, test vector for combination logic. How does it applies in context of testing counter, shift Reg, SPI? d2) Floor planning fiddling is all inside stimulator that can predict timing 'fairly' accurately without actual hardware, right? e) Link for the board is item.taobao.com/…. Very simple. All pins break out to connector, a few LED, switch, buzzer and RS-232. \$\endgroup\$ – EEd Dec 24 '12 at 13:16
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    \$\begingroup\$ Also: fpga4fun.com \$\endgroup\$ – carveone Dec 24 '12 at 13:19
  • \$\begingroup\$ If the data sheet states, says, 200MHz counting frequency, does it refer to BEST CASE performance from experienced designer capable of using FLOOR PLANNING and/or other advanced tools? For learner (likely stict to everything default), what may be the easily achievable speed PERCENTAGE from the data sheet speed? \$\endgroup\$ – EEd Dec 24 '12 at 13:36
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    \$\begingroup\$ @carveone : that book is maybe OK for a complete beginner but subtly wrong in many minor points and badly wrong on some major ones. It'll get you going with some working but ugly VHDL, (what I think of as the "verilog subset") but doesn't even touch on writing cleaner VHDL (almost : it does mention integer subtypes but that's it!). Among free books, Peter Ashenden's "VHDL Cookbook" is probably still the best but tools have advanced a lot since it was written. fpga4fun deserves +1 though. \$\endgroup\$ – Brian Drummond Dec 24 '12 at 16:08
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I'm also a recent start-from-zero CPLD learner. I chose the Digilent Xilinx Coolrunner II dev board.

4 LEDs, 7-seg LEDs, 2 buttons, 2 switches

The reasons I chose it were that Xilinx is a good brand, it was the first CPLD I heard of, the first one I read up on, the price was right, and the dev board is full-featured so I could start learning and not wiring. I was also stunned that small Xilinx CPLDs were about $1 each. Of course, soldering these turns out to be more challenging ;-)

The dev board pictured includes a rather large CPLD, 256 macrocells. This will be good because it will let you experiment without getting fitting errors. If you intend to produce a product, you can get 64 macrocell breakout boards from Dangerous Prototypes for $15 each. They include a button and an LED or two, so it could be a little dev board. Most importantly, however, is that it includes a JTAG header so programming it is easy.

I have shoe-horned my project into 64 macrocells but have not yet loaded it into the DP board; I need more stuff before I can do that, so stay tuned.

The Xilinx products are supposed by the ISE development environment. It's easy enough to use and basically 'compiles' the Verilog (or VHDL) into a binary that can be loaded into the (Xilinx) CPLD or FPGA of your choice.

I don't know the differences between the Xilinx and Altera products. My project is small. If it were discreet old-school chips, it would include a 12 bit counter, a tiny EPROM, a few flip-flops, two 8-to-3 encoders, and a handful of AND and OR gates. It was all I could do to make it fit into a 64 macrocell footprint. In fact, I had to brute-force the fit using a compiler option. Thank goodness that feature exists!

I learned Verilog. From my beginner's perspective, it was a good choice. I am a programmer by trade, so I am unintimidated by Verilog or VHDL. It's all the same to me. I am unaware that either is superior, only that they are different.

Judging by what little I have learned, the 200-600MHz you desire will be difficult to achieve. According to the Xilinx ISE fitter/synthesis software, the maximum clockspeed on my design is 25 MHz. I think it's pessimistic, but that's still a pretty good clip. 100MHz is about the max for the CPLD I am using.

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