Calculating bandwidth for a data bus is like the following in a text I read: "The bus cycle speed is 200 MHz with 4 transmits of 64 bits per clock cycle. The bus bandwidth is then 200*4*64/8=800*64/8 MBytes per second which is 6400 MBytes per second."

But isn't this an appromixation since MHz is 1000 Hz and MBytes is 1024 bytes?

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    \$\begingroup\$ 1 MHz = 1,000,000Hz \$\endgroup\$ – jippie Dec 24 '12 at 15:07
  • \$\begingroup\$ 1 MB/s = 1,000,000 Bytes/s = 8,000,000 bits/s \$\endgroup\$ – jippie Dec 24 '12 at 15:08
  • \$\begingroup\$ 1 MiB = 1024 × 1024 Bytes = 1,048,576 Bytes \$\endgroup\$ – jippie Dec 24 '12 at 15:09
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    \$\begingroup\$ Say "thank you" to Seagate's sales staff anno 1994 or so, they were the first to sell 1MB as 1000000 Bytes because they could charge more for the same disk. \$\endgroup\$ – jippie Dec 24 '12 at 15:10

Yes, it is an approximation. But even ignoring the whole 1000 vs. 1024 thing, it is still an approximation. For future reference, the difference between 1000 and 1024 is 2.4%.

The calculations you show will give you the raw, peak, or theoretical maximum bandwidth. That's the bandwidth you'd get if every clock cycle can be used for transferring data. But that is not always the case. There are many factors which can influence the effective bandwidth.

You didn't say what kind of bus this is, but many buses are used to communicate with some form of RAM, and the same bus is used to transfer the read/write address as well as the read and write data. What this means is that the bus has to switch directions. One cycle the address will be transferred to the RAM, but the next cycle the read data will come from the RAM. It takes time for the direction of the bus to change. Usually one clock cycle, but sometimes more. The worst case scenario would be lots of reads where the following happens: Clock1=Address is sent. Clock2=Direction is changed. Clock3=Data is read. Clock4=Direction is changed again. And then the whole cycle is repeated. In this example, the effective bandwidth is only 25% of theoretical maximum!

Another factor that affects bus bandwidth is read or write latency. I will use PCIe as an example because it is more extreme, but similar things might apply to this bus. With PCIe, a simple 32-bit read might take 2 uS to complete. It is so long because of the serial nature of PCIe as well as the topology of switches and stuff. If your CPU has to do lots of reads, and cannot do anything else while the reads are happening (this is super common) then the CPU will just be waiting. At 2 uS per read, only 2,000,000 bytes/second-- less than 1% of the theoretical maximum for a 1 lane, PCIe v1.0 connection.

Of course we do things to increase efficiency of our buses. We do burst transfers, DMA, prefetching, caching, etc. The efficiency of how we use the bus depends greatly on what we are using the bus for-- the application. I have shown where one application might have only a 1% efficiency, and there are others that might get close to 95% efficiency.

The point is: Yes, the formula you show is an approximation with an error of about 2.4% due to the whole 1000 vs. 1024 thing. But as an approximation, it is fairly close. Especially given the huge difference between theoretical maximum and actual bandwidth.


Not quite.1024 is used only in calculations involving storage/memory space.Quoting wikipeida:

Note that this goes against the traditional use of binary prefixes for memory size. These decimal prefixes have long been established in data communications. This occurred before 1998 when IEC and other organizations introduced new binary prefixes and attempted to standardize their use across all computing applications.


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