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I'm designing a 4-layer PCB that has RF components and digital components. I've decided to use a ground fill only on the portion of the PCB with RF components in order to increase isolation between the microstrip lines. Here's a rendered image of the fully-placed/routed PCB.

enter image description here

In the image, the digital circuitry is on the left and the RF circuitry is on the right. I've used via fences and stitching vias to increase isolation and ensure that I don't get any unintentional antennas. Layers 2 and 3 are unbroken ground planes. The last layer is a signal layer without a ground fill.

I've decided to omit the ground fill from the non-RF portions of the top and bottom layers in order to avoid creating unintentional antennas.

Are there any problems with this layout? I can't think of any, but I haven't seen this done before, so maybe there's a problem I'm not thinking of?

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RF return currents pretty much follow the ground plane directly underneath the outward current path. So on a board as well laid out as this (RF on one side, everything else on the other), a single continuous ground plane across the entire board without splits would not cause a problem. There will be very little interference on the ground plane between the two halves.

Ideally you want unbroken ground underneath our around every digital signal trace to as the high speed edges of the digital signals will induce RF currents. To minimise EMI you want to keep these RF currents as close to their signal traces. You say you've have done this on the inner layers, so that should be fine.

With nice planes on the inner layers, there shouldn't be any major problems with not having a ground plane on the outer layers as shown. I've come across a few boards before that use this approach. Just make sure you place stitching vias between the inner planes any time a digital signal changes layer.

The only advantage of extending the ground plane across to the other side of the board, is that you can add via stitching around the edges of the board. In some cases I've seen boards simply run just a ground trace rather than a full plane around the outside edge of the board on the top and bottom layers, which are then via stitched to the ground plane.

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  • \$\begingroup\$ What's the benefit of adding a ground trace with via stitching at the board perimeter? Does this reduce emissions from fast traces near the board edge? Something else? \$\endgroup\$
    – MattHusz
    Sep 14 '20 at 17:09
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    \$\begingroup\$ @MattHusz it's basically to stop emissions that radiate out from vias within the board - you get RF emissions planar to the PCB, which the grounded vias act as a barrier for. There's an example paper here that discusses it. \$\endgroup\$ Sep 14 '20 at 18:01
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No! Do not do that! Do the OPPOSITE of that! Very nice job with the RF section and via stitching, but ultimately you've gotta give the same priveledge of a ground plane to your FPGA. Especially for product compliance, the noise generated from the high speed signals will waste a $5000 EMI compliance test. By using a huge ground plane and a PCB stackup with thinner spacing between layer top and inner 1, you create parasitic capacitances that look like dead shorts to the high frequency, GHz components of the fast edges of your otherwise slow, X00MHz signal. But worse yet, these edges may get to your RF section through your good idea of an unbroken ground plane in the inner layers. What would be better is to isolate the AC components between your ground planes. Break the inner layer along the interface of the RF and digital domains (really good design separating them!) And in order to connect them, use an inductor between the planes to only pass DC. It's also a good idea to isolate your signal ground from your chassis ground, by turning those mounting holes to unconnected nets. Also don't forget to use the appropriate trace width characteristic impedance calculator for your situation, adding that ground to your RF has given you a coplanar waveguide with ground plane which first of all shouldn't have an inner copper fill (I'm not sure if you implied it did in the RF, too) Because the spacing would be so close so as to shunt all high frequency to ground. Also, be sure that you leave soldermask on your transmission lines, and don't have them as plated pads. ESPECIALLY WHEN DOING ENIG surface finish, holy moly that's a fast way to get disappointed. First of all, the lifetime of the product will experience oxidation which will change the conductivity, thickness, mu, epsilon, basically all your properties will change with oxidation. With ENIG, consider that they needed to apply a nickel layer between the copper and the gold to match the CTE's and lattice constants to get them to stick. Nickel is ferromagnetic, so you'll get attenuation above a few GHz, which could be a good thing, but will ultimately introduce non-linearity into your system which could be unintended. I hope some of that made sense, and if not, ask me to clarify! Sorry about the giant run on sentence!

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  • \$\begingroup\$ I’m not eager to separate the ground planes because I have a few signals between the digital and RF sections, and I don’t want to interrupt their return path. I could provide a separate return path in each case but if I make a mistake somewhere it’s an easy way to add a lot of noise. \$\endgroup\$
    – MattHusz
    Sep 13 '20 at 15:59
  • \$\begingroup\$ Ive accounted for the impedance effect of the ground fill. I used an openems simulation to find that when the gap between the fill and trace is more than about the size of the trace width, it has a negligible effect on impedance. I’ve made it 150% to give some room for manufacturer error. \$\endgroup\$
    – MattHusz
    Sep 13 '20 at 16:04

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