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Whenever I go through datasheets of boost ICs, MCUs, RF power amplifiers, filters, they have recommended designs for best performance.

For example, where decoupling capacitors should be placed or how X track should be as far as possible from Y domain components.

But when I see teardowns of big tech company products, I see tightly packed passive components right next to each other holding hands.

How is that possible? What am I missing? What do those engineers do to put components so close to each other as shown in image below Galaxy watch teardown and still get the best performance out of them? enter image description here EDIT: What are these dashed lines marked by red arrow? seems like separation of analog and digital domain. But how are they achieved in inner layers?

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    \$\begingroup\$ Lots of layers so you can have lots of plane pairs with which to put between signal layers? \$\endgroup\$
    – DKNguyen
    Sep 13, 2020 at 5:07
  • \$\begingroup\$ Lots of layers meaning this tiny smart watch PCB might have 16 or 24 layers? I can't imagine event using 8 layer board can have components this close and get away with signal integrity issues. \$\endgroup\$
    – Curious KP
    Sep 13, 2020 at 5:14
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    \$\begingroup\$ They don’t get the best performance, they just get good enough performance. \$\endgroup\$
    – The Photon
    Sep 13, 2020 at 5:28
  • \$\begingroup\$ It's a recommended design, not required design. \$\endgroup\$
    – user253751
    Sep 14, 2020 at 9:58

3 Answers 3

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Hm, couple of things:

  • "reference design" == "best performance" isn't usually what you need. You need adequate performance, and that might be achievable using smaller layouts.
    • Also, you might have been looking simply at different ICs for other markets than highly integrated designs. I find that nowadays, IC manufacturers put a lot of emphasize on things like "smallest 4A step-up converter design in the world!!!11eleven!", and the reference layouts and layout hints have gone in that direction, too.
    • knowing what you need instead of assuming you want "best" is probably really the key here. That requires a lot of experience and planning. That's why experienced designers tend to be expensive...
  • If you're selling a couple millions of something, you can afford multiple generations of prototypes during design. So, you build a "relaxed" PCB first, then shrink the sections, continuously proving everything still works, until you've reached your desired density.
  • A lot of the rules how much spacing you need is based on "there might be interactions if you're closer than that": There might be. Run an EM simulation of your board, and you'll know.
    • Understanding what your crosstalk does, and where exactly it happens: I don't see an obvious problem with the density of the devices in your photo: sure, all these capacitors are close by. But the majority of these are decoupling caps, and cross-coupling into these isn't as terrible. They're literally meant to absorb variations! Also, the currents there flow mostly between the surface of the board and the underside of the capacitor contacts – not a very large area where you can interfere with your neighbor.
  • More layers. Seriously. Layers do wonders. Dedicated power layers with a protective ground/low speed power layer can effectively isolate power and signal.
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  • \$\begingroup\$ Can you also tell me about red arrow marked areas, How is that achieved in actual design? Is it just exposed copper? What about internal layers under that. \$\endgroup\$
    – Curious KP
    Sep 19, 2020 at 2:09
  • \$\begingroup\$ if you mean the solder-silver areas: yeah, just a copper plane (good chances: ground) exposed. \$\endgroup\$ Sep 19, 2020 at 8:05
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  • Those large foil layers become magnetic shields for frequencies faster than about 1MHz (just a few dB reduction), with 4MHz getting 9dB (1 neper), 40 MHz getting 27 dB (3 nepers), 160MHz (typical MCU edge speed or VDD ringing) getting 50--60dB attenuation, and 400MHz (sub_nanosecond edges) getting 80--90 dB attenuation (10 nepers or 90dB).

  • One way to cause lots of problems is to SHARE the +3.3 volt (or +2.5v) or +5volt copper foil, everywhere in your electronic system.

By sharing, rail_trash from one IC becomes rail_trash for all the other ICs, and the PSRR power supply rejection at high frequencies becomes a crucial spec.

  • By inserting series resistors, 1 ohm or 3.3 ohm or 10 ohms, in selected places, the VDD foil becomes a VDD_TREE. Note that 10 ohms and 1uF becomes a 10uS timeconstant and a 16KHz low pass filter, able to attenuated SwitchReg trash by 100:1, and attenuated MCU VDD ringing by possibly 10,000:1 (limited by the capacitor ESR and ESL). Thus small_value resistors IN SERIES in the VDD traces can significantly clean up VDD trash, for crucial sensor ICs.

For a long time (many decades), I've called the R+C filtering of VDD the "local battery", which ensures the local fast charges are all locally_provided; this prevents irksome ground loops.

Here is link to design_of_ground_planes

Should I really divide the ground plane into analog and digital parts?

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  • \$\begingroup\$ Can you elaborate more on "By inserting series resistors, 1 ohm or 3.3 ohm or 10 ohms, in selectric places, the VDD foil becomes a VDD_TREE."? Do you mean converting this in star topology with each branch is different IC, Having its own RC filter for localized filtering of interference creeping in through power rails? \$\endgroup\$
    – Curious KP
    Sep 13, 2020 at 17:29
  • \$\begingroup\$ Can you also tell me about red arrow marked areas, How is that achieved in actual design? Is it just exposed copper? What about internal layers under that. \$\endgroup\$
    – Curious KP
    Sep 19, 2020 at 2:09
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Someone once told me that anyone can build a bridge that stands. But it is much harder to build a bridge that "barely" stands.

Engineering is all about trade offs and making something that is good enough. As the surface area shrinks it can lead to more issues with signaling.

Most designers will spend more time on part placement to try to minimize the the crossing of signals.

It can be helpful to make a list of "aggressor" and "victim" signals. This way you can identify which signals need to be carefully monitored during signal routing.

Depending on whether the signal is an aggressor or victim (and a signal can be both!) we then might decide how we want to alter it to optimize the layout.

For example we may bury a signal on an internal layer to protect it from external radiation but this might be at the cost of more loss and changing the impedance as the signals passes through a via.

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  • \$\begingroup\$ Can you also tell me about red arrow marked areas, How is that achieved in actual design? Is it just exposed copper? What about internal layers under that. \$\endgroup\$
    – Curious KP
    Sep 19, 2020 at 2:09
  • \$\begingroup\$ Do you have a link for where you got this image? I'd like to do some digging to see if i can make an educated guess \$\endgroup\$ Sep 22, 2020 at 20:41
  • \$\begingroup\$ ifixit of samsung galaxy watch ifixit.com/Teardown/Samsung+Galaxy+Watch+Teardown/117519 \$\endgroup\$
    – Curious KP
    Sep 22, 2020 at 20:47
  • \$\begingroup\$ In the picture below it looks like those are solder points to tie the chassis to an inner layer to make a nice faraday cage. They may also be floating solder poitns depending on the engineer's preference. \$\endgroup\$ Sep 22, 2020 at 20:59
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    \$\begingroup\$ Yeah it is probably a solid ground layer. \$\endgroup\$ Sep 22, 2020 at 21:36

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