I have an array of 110 digital pins and I need to route the pins with one-way channels through a series of multiplexers such that the following conditions will always be true:
- Each pin will have a channel/path to exactly one other pin
- Each pin may be either an input or output from one configuration to the next but will only be an input or output for any one configuration (a unidirectional channel/path).
- Due to the above two stipulations we can assume exactly half of the pins are input and half are output during any one configuration.
- All pins are digital.
- Either all pins are 3.3V logic or all pins are 5V logic, we dont know which it is ahead of time
- No pin will connect back on itself (this should be common sense but worth mentioning)
- The time it takes to reconfigure the network is not important, it can be slow.
- The configuration of the network should be controllable via an atmel, this atmel will not be the chip that connects to the 110 digital pins itself, only to control the multiplexer configuration. As such the number of pins needed to configure the network needs to be reasonable.
- Any solution should be able to fit on a 10cm x 10cm PCB, though it can have multiple layers.
- Propagation delay of a signal through the multiplexer, once the multiplexers have been configured, should be minimized. I do not have a specific minimum delay I can quote but getting this number as low as possible should be a priority.
- I list some parts below that I am currently using in my attempted solution, but there is no need that I need to use those specific parts. I can consider solutions using entirely different parts if they achieve the intended goal better. In fact if I cant get this approach to work I am even considering moving to an FPGA, however the main reason I am not is because they are all BGA packages and they would be a nightmare to work with in a prototype.
My Attempted solution
So I identified a few chips that I should be able to create a solution if I can find the right way to connect them all together. They are as follows.
Parts Being Considered
This is a chip with a single 32:32 digital (one way) multiplexer on it that is configurable through I2C. It has 1,024 channels so it is capable of routing any of its 32 inputs to any of the 32 outputs. It is expensive at about 25$ per chip so ideally I'd like to make it a priority to minimize the number of these chips I need in my solution.
This is a chip with three 1:4 analog (two-way) multiplexers on it and is also configurable through I2C. These are relatively cheap at about a dollar or two so I dont mind having several on the board should they fit.
This is a chip with one 1:8 I2C switch on it. It allows you to have 8 separate "sub-networks" of I2C devices so you can address the issue of I2C address conflicts by putting conflicting addresses in different I2C subnetworks. These are also relatively cheap so I dont mind if I need three or four of these.
Finally any sort of microcontroller capable of controlling the multiplexers, this will not be connecting to the 110 digital pins only talking to the multiplexer array to configure it.
So my current way of tackling this, which keep in mind isnt really working out, is to have 2x32:32 digital multiplexer chip. It would have 32 inputs and 32 outputs on each chip. While by itself it would be capable of routing any pins in a group of 32 to any other pins in the same group that wont get me very close to handling 110 pins. My solution at first was to use the 1:4 analog multiplexers such that each multiplexer had its single side connected to one of the digital pins. The four output pins of the analog multiplexer would be connected to a pin as such, where A represents one of the 32:32 multiplexer and B represents the other one: an input on chip A, an input on chip B, an output on chip A, an output on chip B. My hope was if I selected the right pin arrangement between the analog and digital multiplexers I could achieve the result I wanted.
The problem is I cant find a configuration with this setup that actually can achieve my goal. The closes configuration I found would work to successfully route in any configuration 64 digital pins, but beyond that the topology has edge cases where it would fail. The problem with my solution that works for 64 pins is that more than half the pins on the 2x32:32 multiplexers would go completely unused for any configuration. So while I could scale this solution up to work by using 4x32:32 multiplexers this would significantly increase the cost to make this and would waste half the pins on the 32:32, so ideally I'd like to find a solution that is more affordable. I will need some sort of a new configuration but im struggling to figure out a way to do this well.
For reference here is the approach I would use that would work for up to 64 pins: