I have a 74LS76 JK flip flop hooked up as follows:

enter image description here

You think that should be easy. But look at my scope traces of Q above and Q-bar below:

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how the heck can a JK flip flop's output Q and Q-bar be not completely complementary?

Here is Q above against the CLK below if it helps figuring that one out.

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Even if this is falling edge triggered, this should not happen!

Clock is 4 MHz.

More scope traces requested in comments:

Here is both probes in Q:

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here is !Q against CLK: enter image description here

Q against (Q AND !Q) (AND - 74HC08) enter image description here

!Q against (Q AND !Q) enter image description here

CLK against (Q AND !Q) enter image description here

So you can see, this is real, not an issue with the scope. It's also a fairly isolated test so not much could go wrong. The wiring checked and double checked.

  1. pin 1 = CLK
  2. pin 2 = H
  3. pin 3 = H
  4. pin 4 = H
  5. pin 5 = H (Vcc)
  6. pin 6 = pin 1
  7. pin 7 = H
  8. pin 8 = pin 3
  9. pin 9 = pin12
  10. pin 10 = NC (2Q)
  11. pin 11 = NC (2!Q)
  12. pin 12 = RCO of 74LS161 #2 - or H for same test on JK FF #2 of same chip
  13. pin 13 = GND (L)
  14. pin 14 = NC (1!Q)
  15. pin 15 = NC (1Q)
  16. pin 16 = H

bypass cap 100nF riding between pin 5 and 13

This is read from the wiring, not from the schematics.

Here is the chip, I am in Brazil, and so I'm stuck with what I'm getting here.

enter image description here

I don't think that ground bounces are the issue since I check my power rails with the scope too and it is just too reproducible with this chip.


I would have to get another '76, which I will try. Meanwhile I tried the '74 and it is almost working with that, except the high stage that is supposed to toggle when the ripple-carry-output of the '161 is high and the next clock pulse comes, that isn't working right. It would toggle too early. I had to make a poor man's AND gate with resistor diode and that would mess things up anyway. If I use a real AND gate then I'm going to have switching delays again.

I guess I haven't paid attention to that previously, I need to trigger that on the falling edge of the RCO, so maybe I need to get a falling edge triggered JK ff anyway. Let's figure this out:


I'll run now before the store closes here.

BACKGROUND ONLY: I have a 16-bit counter, 74LS161, it runs at 4 MHz now but I want to get it to work with 16 MHz. The counter value becomes RAM addresses, and for that application I found that glitching is a major problem. So I moved from async 74LS393 with 74HC4040 to 4 74LS161 counters.

For the correct derivation / switching of the counter values to become the RAM addresses, I require bit 0 (LSB of low byte) and bit 8 (LSB of high byte) to exist in both straight and inverted form. But, if I use an inverter to invert this bit, then the follow-up address selection logic glitches because of the delay of the inverted LSB.

I thought I had a solution by running the LSB as a parallel JK flip flop which would be clocked by the same clock, or an prior inverted clock, depending on whether the JK ff is rising vs. falling edge triggered. Here is a piece of the schematics using the 74LS78 JK flip flops:

enter image description here

sorry for the vertical arrangement and low resolution. Anyway, right now what matters is just the JK flip flop.

If I use the 74LS78 I have it glitching on the high stage, in such a way that Q and Q-bar flip over even just by me putting the scope probe in one or the other, and if both are tied as inputs to the following AND gate(s), they end up rapidly flipping around.

Now I gave up on the 74LS78 and used the '76 instead. With the problem as initially stated.

  • \$\begingroup\$ Just spending one minute on this, so far, I can see that the absolute maximum specification (and I would under no circumstances try it) is \$25\:\text{MHz}\$ for the clock input. This is assuming there's only \$15\:\text{pF}\$, the temperature is room temp, low impedance drive, and the supply voltage is \$5.5\:\text{V}\$. That goes down to \$20\:\text{MHz}\$ at \$50\:\text{pF}\$. It wouldn't take much to push you below your goal. Just want to make sure the rest is right before looking over your details here. Can you let us know? \$\endgroup\$
    – jonk
    Sep 14, 2020 at 3:01
  • \$\begingroup\$ @jonk, this is currently clocked at only 4 MHz. \$\endgroup\$ Sep 14, 2020 at 3:37
  • 3
    \$\begingroup\$ Is the scope trigger set to alternate, or chop? Can you try a D flip flop instead (eg. 74LS74)? \$\endgroup\$ Sep 14, 2020 at 3:56
  • 3
    \$\begingroup\$ @GuntherSchadow: Set your scope to "chop" instead of "alt." You have an analog oscilloscope with a single electron gun. To display two traces, it has to simulate two guns. It has two methods to do that. "Alt" means that it shows each trace on every second sweep. You cannot view synchronized signals that way - there will always be a time shift between channels. "Chop" shows both traces in one sweep so that they are synchronized, but it switches back and forth between the two rapidly in one sweep. Youcan see synchronized events but you lose bandwidth. \$\endgroup\$
    – JRE
    Sep 14, 2020 at 5:41
  • 3
    \$\begingroup\$ Connect both probes to Q. See if you still get an offset. Switch between "alt" and "chop" and see if the offset goes away. \$\endgroup\$
    – JRE
    Sep 14, 2020 at 6:10

1 Answer 1


Indeed this was a bad chip! It functioned almost perfectly fine, no issues except the switching was not right. I went and bought another one for an eff-ton of money 4 USD -- twice the price of a kilo of strawberries -- and behold:

enter image description here

Note how much more smooth the traces are. Not that it would necessarily matter, but clearly it behaves differently than the first chip.

This new one is also a TI make, but looks nicer. Not sure if the other one was a Chinese fake?

enter image description here


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