I have a 74LS76 JK flip flop hooked up as follows:
You think that should be easy. But look at my scope traces of Q above and Q-bar below:
how the heck can a JK flip flop's output Q and Q-bar be not completely complementary?
Here is Q above against the CLK below if it helps figuring that one out.
Even if this is falling edge triggered, this should not happen!
Clock is 4 MHz.
More scope traces requested in comments:
Here is both probes in Q:
So you can see, this is real, not an issue with the scope. It's also a fairly isolated test so not much could go wrong. The wiring checked and double checked.
- pin 1 = CLK
- pin 2 = H
- pin 3 = H
- pin 4 = H
- pin 5 = H (Vcc)
- pin 6 = pin 1
- pin 7 = H
- pin 8 = pin 3
- pin 9 = pin12
- pin 10 = NC (2Q)
- pin 11 = NC (2!Q)
- pin 12 = RCO of 74LS161 #2 - or H for same test on JK FF #2 of same chip
- pin 13 = GND (L)
- pin 14 = NC (1!Q)
- pin 15 = NC (1Q)
- pin 16 = H
bypass cap 100nF riding between pin 5 and 13
This is read from the wiring, not from the schematics.
Here is the chip, I am in Brazil, and so I'm stuck with what I'm getting here.
I don't think that ground bounces are the issue since I check my power rails with the scope too and it is just too reproducible with this chip.
I would have to get another '76, which I will try. Meanwhile I tried the '74 and it is almost working with that, except the high stage that is supposed to toggle when the ripple-carry-output of the '161 is high and the next clock pulse comes, that isn't working right. It would toggle too early. I had to make a poor man's AND gate with resistor diode and that would mess things up anyway. If I use a real AND gate then I'm going to have switching delays again.
I guess I haven't paid attention to that previously, I need to trigger that on the falling edge of the RCO, so maybe I need to get a falling edge triggered JK ff anyway. Let's figure this out:
- 74LS76 - DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR
- 74LS78 - DUAL J-K FLIP-FLOPS WITH PRESET, COMMON CLOCK, AND COMMON CLEAR
- 74LS112 - DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOPS WITH PRESET AND CLEAR
I'll run now before the store closes here.
BACKGROUND ONLY: I have a 16-bit counter, 74LS161, it runs at 4 MHz now but I want to get it to work with 16 MHz. The counter value becomes RAM addresses, and for that application I found that glitching is a major problem. So I moved from async 74LS393 with 74HC4040 to 4 74LS161 counters.
For the correct derivation / switching of the counter values to become the RAM addresses, I require bit 0 (LSB of low byte) and bit 8 (LSB of high byte) to exist in both straight and inverted form. But, if I use an inverter to invert this bit, then the follow-up address selection logic glitches because of the delay of the inverted LSB.
I thought I had a solution by running the LSB as a parallel JK flip flop which would be clocked by the same clock, or an prior inverted clock, depending on whether the JK ff is rising vs. falling edge triggered. Here is a piece of the schematics using the 74LS78 JK flip flops:
sorry for the vertical arrangement and low resolution. Anyway, right now what matters is just the JK flip flop.
If I use the 74LS78 I have it glitching on the high stage, in such a way that Q and Q-bar flip over even just by me putting the scope probe in one or the other, and if both are tied as inputs to the following AND gate(s), they end up rapidly flipping around.
Now I gave up on the 74LS78 and used the '76 instead. With the problem as initially stated.