transimpedance amplifier based on a capacitive feedback current amplifier

I am trying to understand the circuit in this publication. The picture below is the simplification of the circuit. I do not understand the role of the cascode configuration part of the circuit. Appreciate any inputs or reference to other publications that similar with this.

From the paper, the whole circuit is a transimpedance amplifier which is based on a capacitive feedback current amplifier. The output current is dumped into the load resistor to get the output voltage which is later buffered.

There is other circuit which I think is similiar, but using single ended opamp here. Here is the picture.

The cascode stage is there as a transconductance to convert the voltage output from the gain stage to a current that can be directed to the current steering network (that you have omitted from your diagram) to achieve gain control.

The differential cascode stage is convenient in that it has the other leg for use as the actual output for the circuit.

Your second circuit is not really the same as it uses a voltage output stage. M2 is just there as a buffer.

Note that where capacitative feedback is used some means of ensuring stable bias must be present. In the first circuit there are resistors (that you have not shown) that do this.

• Thank you for your answer. So can I think of it as a fully differential two stage amp (1 V2V amp + 1 V2I amp) whose one output (leg) is used as sampling point and one as actual output? it seems really strange to me. Do you have any reference that I can learn from or keywords so I can look up? I have access to some analog CMOS ic books and ieee. Commented Sep 14, 2020 at 22:09
• @Codelearner777 - I've never seen that technique used in an amplifier but the current-steering approach is a very old and common one in fast DACs. Commented Sep 14, 2020 at 22:19
• hi...is there any specific name of the comfiguration where one leg of differential stage is used as a sampling point for feedback and the other as the actual output? Commented Sep 17, 2020 at 9:31

The cascade stages are to reduce Miller Input Capacitance.

Lower capacitance allows high bandwidth, yet needs low Iddq.

I recall designing a ADC_clamp, with active servoing to hold the ADC summing node within 10 milliVolts of Ground, instead of 0.3 or 0.6 volts (schottky or regular diode clamps).

My active clamp was way too slow. A year later, after a course in opamp circuitry (internal), and various opamp topologies, and stability/Bode training, I also understood Miller Effect was my oversight.