When the AND gates run out, and I just need one more, I like to use a "wired" gate, simple resistor-diode logic. Here is AND
and here is OR
Now for the pull-up resistors, I use just 1 kΩ normally. But I am wondering about contention by current flowing back into the inputs. I know if the input has no fan-out, so, if A and B come out of their own gates and are not also routed to be input into another gate, then there is no problem.
I also know that normally one should do this with open-collector gates. But again, at 1 kΩ pull-up for the AND it's probably not going to hurt, I don't think.
But does it confuse other inputs parallel to A? Example, I'm using buffer symbols for whatever TTL devices I might use here, doesn't matter.
The question is if G4's input is not by accident pulled high by this diode? Or is there a magic R1 value that might prevent this from happening? I know that 10 kΩ might be too much to even pull up the input of G3. But what about 2.2 kΩ?
Certainly this has to do with the specific device families. But are there common values considered safe for 74LS* and 74HC* respectively? And certainly pull-up for AND and pull-down for OR will have different sweet spots. I suppose the bigger the fan-out of the upstream outputs, the less it will matter.