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When the AND gates run out, and I just need one more, I like to use a "wired" gate, simple resistor-diode logic. Here is AND

enter image description here

and here is OR

enter image description here

Now for the pull-up resistors, I use just 1 kΩ normally. But I am wondering about contention by current flowing back into the inputs. I know if the input has no fan-out, so, if A and B come out of their own gates and are not also routed to be input into another gate, then there is no problem.

I also know that normally one should do this with open-collector gates. But again, at 1 kΩ pull-up for the AND it's probably not going to hurt, I don't think.

But does it confuse other inputs parallel to A? Example, I'm using buffer symbols for whatever TTL devices I might use here, doesn't matter.

schematic

simulate this circuit – Schematic created using CircuitLab

The question is if G4's input is not by accident pulled high by this diode? Or is there a magic R1 value that might prevent this from happening? I know that 10 kΩ might be too much to even pull up the input of G3. But what about 2.2 kΩ?

Certainly this has to do with the specific device families. But are there common values considered safe for 74LS* and 74HC* respectively? And certainly pull-up for AND and pull-down for OR will have different sweet spots. I suppose the bigger the fan-out of the upstream outputs, the less it will matter.

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  • \$\begingroup\$ LS (TTL) and HC (CMOS) have very different requirements. LS will have different requirements for wired OR compared to wired AND. Note I’ve given you this hint, can you figure out why? \$\endgroup\$
    – The Photon
    Commented Sep 15, 2020 at 5:07
  • \$\begingroup\$ @ThePhoton, I know that the requirements are different, I said so in my question. And my question is asking for what those requirements are one by one LS/HC x pull-up-AND/pull-down-OR. \$\endgroup\$ Commented Sep 15, 2020 at 15:39
  • \$\begingroup\$ Your resistor is simply a load. If you look in the electrical specifications, you'll see allowed loading and performance against it, ie, the output voltage in the presence of a load resistance or load current, in both positive or negative directions. \$\endgroup\$ Commented Sep 15, 2020 at 15:52
  • \$\begingroup\$ @ChrisStratton (re your now del/edited comment) Diodes in the path directed away from the result towards the input will only let a low through to bring the voltage to GND + diode voltage drop. If input is high, diode is shut off and result is high. If pull-up R is low, e.g., zero, it will drive the input and all its fan-out siblings high. If diode is directed from input to output, diode only lets a high through, pushing against the pull-down resistor. If the resistor is too low, e.g. zero, the diode would short the inputs (and all its parallel fan-out siblings) to low. What am I missing? \$\endgroup\$ Commented Sep 15, 2020 at 15:56
  • \$\begingroup\$ You're missing that the resistor is a load, and the performance against a load is characterized in the data sheet. Build a lighter load than the one for which the data sheet implies suitable performance. \$\endgroup\$ Commented Sep 15, 2020 at 15:58

2 Answers 2

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I use just 1 kΩ normally. But I am wondering about contention by current flowing back into the inputs.

You need to look at the datasheets for the gates whose inputs you are driving. For example, a typical 74LS04 datasheet specifies 20 uA input current when high (\$V_I = 2.7\ {\rm V}\$) and -0.4 mA input current when low (\$V_I = 0.4\ {\rm V}\$).

So for a pull-up holding up a single LS family load, assuming a minimum supply voltage (4.5 V), the maximum resistor value \$\frac{4.5-2.7}{20\times10^{-6}}= 90\ {\rm k\Omega}\$.

For a pull down you need \$\frac{0.4}{0.4\times10^{-3}}= 1\ {\rm k\Omega}\$ or lower (actually a fair amount lower is better since you can't count on the driving gate to pull absolutely all the way to 0 V). Once you've done a couple calculations, though, you'll probably find the results are re-usable for similar combinations of gates in the same family.

For a different logic family, or for multiple gates loading the circuit, you will need to calculate new values based on the total leakage current into the gates.

The question is if G4's input is not by accident pulled high by this diode? Or is there a magic R1 value that might prevent this from happening?

No. When G1's output pulls low, it pulls G4's input low, regardless of R1 (assuming R1 isn't so low that G1 can't provide enough current to pull it low). When G1's output is high, the diode is reverse biased and so R1 is irrelevant to the voltage at G4's input.

But are there common values considered safe for 74LS* and 74HC* respectively?

Many people do sloppy designs. If you want to get it right, you should review the datasheets of the gates you're actually using and determine the appropriate resistor values.

I suppose the bigger the fan-out of the upstream outputs, the less it will matter.

The bigger the fan-out of your wired gate, the lower your pull-up/down values will have to be.

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Checking the data sheets is certainly true.

What I found is that theory and practice differ. That is why only things tested in practice can really be relied upon.

I found that the wired OR did not work for one use case under any circumstances. It was supposed to drive low the !PRE pin of a 74LS76 when two inputs were low. I found that whatever pull-down resistor I use, even as low as 100 ohm, it does not drive the !PRE input low enough to cause any effect.

Earlier consideration:

I base my answer on the observation that even in TTL logic, there is some current flowing backwards through the base - emitter pathway out from the inputs. So maybe my answer is R1 = 4 kΩ for a pull-up:

enter image description here

if anything a switching diode would have less resistance than this base - emitter path of V1 in the TTL circuit. That would mean that I should try even higher.

I will just have to do it by trial and error, starting with 10 kΩ, and go down the standard series ... 8.?, 5.6, 4.7, 3.3, 2.2, down to 1 kΩ.

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    \$\begingroup\$ Trial and error is not needed, the performance of the output in the presence of a load will be characterized. The load which a following stage presents on your pulling resistor will also be characterized. \$\endgroup\$ Commented Sep 15, 2020 at 15:59

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