0
\$\begingroup\$

I have code that checks all kind of input parameters with VHDL Assert statments like the following:

assert 2**size >= OneHot'length
report "oneHot_binary: Output vector to short."
severity failure;

When testing the code with Modelsim and CocoTB, the simulation stops on error (as expected). Is there a way to inform CocoTB about such an event? I would like the test to fail instead of the simulation to stop.

\$\endgroup\$
  • \$\begingroup\$ You can change the severity level to Error, and separately control whether Modelsim stops on Error or continues. \$\endgroup\$ – Brian Drummond Sep 15 at 15:40

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.