My RTL viewer replaces NAND gates with AND gates with the inversion bubbles

I want it to show this MUX only with 3 NAND gates and an Inverter. so, I specified NAND gate in the verilog HDL code, but it keeps replacing it with AND gates with inversion bubbles without having a single NAND gate. I want to fix this problem. I have to get NAND gates out of it. please let me know if you have any idea.

• 1. It would probably help to know what program you are using. 2. If your target is an FPGA, it all gets turned into LUTs in the end, so who cares whether it gets drawn as ANDs or NANDs here? – The Photon Sep 16 '20 at 2:21
• Same thing happens in verdi which I'm using to check the schematic. I don't know what tool you're using, but I think either you find a switch (if there is) in your setting dialog, or create a named net for each intermediate expression. Since HDL just describes the truth table of combinational logic, the implementation tool will optimize it as long as the truth table still holds. It really doesn't matter how it is shown. – Light Sep 16 '20 at 2:28
• Learn to love the bubbles. They are all AND gates. The bubbles make explicit which polarity of inputs, when AND'ed together, form the output, which then may or may not have a bubble. It looks screwy at first but once you get used to it you won't want to go back. – td127 Sep 16 '20 at 3:36
• w0 and w1 are both NAND gates ... the output inversion is stuck to y inputs ... y is a NAND gate, the output inversion is at y~not – jsotola Sep 16 '20 at 3:51
• I downloaded QuartusLiteSetup-15.1.0.185-windows, ModelSimSetup-15.1.0.185-windows and cyclonev-15.1.0.185.qdz. And this is when verilog HDL code runs on them. – esse non videri Sep 16 '20 at 4:44