I want it to show this MUX only with 3 NAND gates and an Inverter. so, I specified NAND gate in the verilog HDL code, but it keeps replacing it with AND gates with inversion bubbles without having a single NAND gate. I want to fix this problem. I have to get NAND gates out of it. please let me know if you have any idea.
While you can build everything from NAND Gates - these are the most universal - and I guess that is why you want to see em, NAND Gates are not the lowest reduction level of a boolean equation. And this is what your tool will do - it reduces the boolean equation to a optimal point prior to synthesis.
The Goal is to replace the found solution with FPGA LUTS and glue logic or optimized gates of a library of a factory like TSMC... the least thing you want to have is all NAND gates here