I am trying to figure out the best practice for implementing a reset (async applied, sync cleared) and a clear input. I have a process that must run off a logic-derived clock (NCO) that is called code_clk, slower but synchronous to the actual clk. The process involves a Linear Feedback Shift Register that must reset to all 1's to begin a code generation sequence after the reset is lifted. However, throughout operation the process should also reset to all 1's when a new set of taps (T1 and T2) are selected for the output, of course in order to reset the code generation sequence and make sure the new code is valid with the new taps. This is done with a separate, synchronous clr input that gets held high for a single system clock cycle while the taps are moved around.
Here is my code:
process(code_clk, reset, clr) begin if(reset='0' or clr='1') then -- EARLY LFSR EG1(1 to 10) <= (others => '1'); EG2(1 to 10) <= (others => '1'); early_code <= '0'; delay_os <= '0'; elsif(falling_edge(code_clk)) then if(delay_os='0') then -- LFSR feedbacks for early code EG1(2 to 10) <= EG1(1 to 9); EG2(2 to 10) <= EG2(1 to 9); EG1(1) <= EG1(3) xor EG1(10); EG2(1) <= EG2(2) xor EG2(3) xor EG2(6) xor EG2(8) xor EG2(9) xor EG2(10); early_code <= EG1(10) xor EG2(T1) xor EG2(T2); -- C/A output of early LFSR else -- delay of code chips commanded - do not shift this time delay_os <= '0'; end if; late_code <= early_code; -- one half chip delay from prompt code elsif(rising_edge(code_clk)) then prompt_code <= early code; -- one half chip delay from early code end if; end process;
The conditional if(reset='0' or clr = '1') kind of jumps out at me as being bad style. It just seems like one of those situations where synthesis will produce unnecessary logic or timing delay because the reset path is not as straightforward. Can I do this or should I try something else? The clear needs to happen immediately so I'd either need to make the process run off of the system clock or something else. Is this considered good practice?