# Flip-flop circuit variation

I am having troubles understanding how the following circuit works. It is from the AoE book 3rd ed. p. 196 Fig. 3.99C.

I added the resistor in red myself as I assume it was missing from the schematic (maybe I am wrong).

Here what authors tell about the circuit.

This circuit is a bit tricky, because you have to juggle several time constants appropriately*. But the basic concept is simple, and elegant: charge a capacitor from the inverted output of the flip-flop’s control input, then momentarily connect the charged capacitor to the control input to make it toggle.

*The capacitor’s charging time to the new state τC=R1C1 should be ∼100 ms to allow for switch bounce; R3C1 should be much shorter, and the discharge time constant of output transistor’s gate capacitance (R3 +R4)Cg should be faster still. Here we chose 100 ms, 2 ms, and ∼0.4ms, respectively.

Could anyone please explain in step-by-step manner, starting from the OFF state, then 1st button press, then 2nd and return into OFF state again? (With all the voltages and names of the components).

Well at the beginning we have this situation:

C1 capacitor is discharged hence 0V across it and all-transistor of OFF.

But if we press the switch we momentarily connect the discharged capacitor with the Q1 gate. But since Q1 is a P-channel MOSFET thus a low voltage at the gate Turns-ON the MOSFET. If so, The voltage at Q1 drain jumps from 0V to +9V which Turns-ON Q2 and Q2 Turns-ON Q3.

At the same time due to voltage rise at Q1 drain from 0V to +9V the C1 capacitors begin the charging phase via R1 and R3 (if the switch is still pressed). Also, notice that the switch is no longer needed to be press because now the circuit is latched. Q1 opens --> Q2 and now Q2 will provide a low state needed for Q1 to be open (and stays open). So, we end up with this:

C1 is fully charged by R1 to 9V and all MOSFET's are ON because Q1 and Q2 form a latch.

Now I hope that you see what will be going to happen next.

If we press the switch again (C1 is fully charged to +9V), for a very brief moment of time this 9V "will appear" at the Q1 gate (we momentarily connect the charged capacitor to Q1 gate). And the High state at Q1 gate will of course Turn-OFF the Q1 MOSFET and the voltage at the Q1 drain will drop imminently to around 0.2V so the Q2 will also Turn-OFF and Q3 as well. C1 will be "slowly" discharge via R1 and R2.

And this is the end of a very "brief" description.