# Confusion about open-drain for I2C

Just some clarification on the open-drain concept for I2C.

Open-drain configuration is used mainly to avoid any sort of short circuit in case one device is one line is being pulled low by one master while the other master is pulling the line high. And how it works is by whichever master pulls the SDA line low first gets to control the slaves, and by pulling the SDA line low in this diagram means setting the gate voltage of the MOSFET high, isn't it? Because when it's high, the output/drain is pulled low. If that's the case, why is the gate labelled as SCKN1 OUT as opposed to SCKN1 IN?

• I'm not sure I understand the question--it's the output, not the input, so it's called out, not in. – Hearth Sep 19 at 2:44
• I know. My confusion was about why the gate is labelled as output – xyf Sep 19 at 18:08

Your reasoning isn't quite right. The open drain configuration is used so that any line can be an output and an input, even both at the same time. So, to read the state of SCLK you look at SCLK IN. If you want to drive SCLK you drive SCLKN1 OUT. Obviously, if you drive SCLK low, you will read back a low signal. But if you "drive" it high (actually you release it), then by reading the input you can find out if it really is high, or if another device has driven it low.

It is difficult to tell from your comments where the misunderstanding lies. So let's look at a few facts to see if we can find it.

• The drawing doesn't say which device is master. Either one could act as master. Or a master may be somewhere else but not shown. From a protocol standpoint it doesn't really matter which it is.
• Each device is going to have the necessary circuitry to read the IN's and set the OUT's. This may be a micro controller (mcu), but doesn't have to be. Let's assume they are, for simplicity. Wherever the master is, it has an mcu there, connected to its INs and OUTs, and no one else's. The only things tied together are the bus signals on the other side of the buffers and FETs.
• The meaning of OUT is, "I want to OUTPUT a LOW state on the bus". Choosing the name of a signal presents many choices. Consider that the software executes an out instruction that sends out a signal on an I/O pin, which is then routed to the input of an FET, which responds by sending out a low signal on the bus, where the other devices look at the signal routed into the read buffers, which output the state of the signal to the mcu I/O pin that's configured as an input to read in the state.
• The notion that the master is the only one driving (outputting to) the bus is incomplete. The slave device will drive SDA low to create the ACK. It will also control SDA when data is being read from it. In addition, devices have the option of pulling SCLK low if they need more time to get their data ready. The master releases SCLK to high and if it doesn't read back as high, then "clock stretching" is in effect. This is slightly more advanced, but it is very real, especially if the slave device is operated by an mcu.

So, in the big picture, each device must be able to control both bus lines, and be able to read their state back at the same time. And make sense of it all.

• my point was about the output pin that we are driving vi software: the gate of the FET gets set when we set the SDA low for instance, yes? If that’s the case, shouldn’t the gate be labelled as input since that’s being controlled by the software? – xyf Sep 19 at 14:23
• Your point is valid, but many times there are many choices how to describe something. And "they" (whoever made the drawing) don't always choose the best name. Comments in a program can also be like this. You might say "set SDA low", but instead you might say, "initiate a Start sequence". Both are correct, but one may tell a better story. Also, when I'm new to something, I tend to look at details like transistor gates, and later on I look at big-picture concepts like Start or Ack. – gbarry Sep 19 at 19:04
• what's your understanding behind OUT being used as the gate voltage given it's controlled via software? also, the SDA/SCK lines are controlled by the master. Now how does the master control the lines if the gate voltages of the FETs aren't connected to the master's FET (which isn't shown here)? that's prolly causing confusion in my understanding – xyf Sep 20 at 1:31

I feel I don't understand the relation between the paragraph of description and the last question clearly.

Open-drain output plus wire-and work with some concepts in I2C system perfectly. With open-drain output, one device can output LOW. And when it is going to output HIGH, it just gives up driving the line, let the external pull-up path do that. Because there is no damage when multiple devices output LOW concurrently, we can easily expand the system by simply attaching a new I2C device to the SDA/SCL bus. Each device is listening to the bus via its own input path all the time. So they can detect bus collision if the read back value from line is not equal to what it is sending. The device who detects a collision loses arbitration, and quits transmission silently which will not introduce any overhead to the entire system. The same idea is used in CAN system.

In the picture, the MOSFET is used to output signal SCLKN1 OUT. And collision is detected by checking the input signal SCLK IN.

(Struggling my english. Hope I made it clear.)

The I2C output driver FETs are doing just that: driving the outputs to a chosen voltage. Other devices will detect that line voltage level through input logic gates.

Signals are named for the direction of the signal itself, not for the direction of the current flow.

The fact that the driver actually inputs and sinks current from a pull-up resistor to do it is therefore irrelevant. A push-pull output driver is sourcing current when driving high and sinking it when driving low but it's always called an output.

• Maybe this picture is not complete and misses other components like master? Or wait, the output driver in the master should be the one controlling the SDA/SCK lines isn’t it? Then it makes me wonder as to what controls the gate voltage of the slaves’ FET driver. Also, where’s push-pull config that you’re referring to in this image? Isn’t this supposed to be open drain only? – xyf Sep 19 at 14:32
• You've not understood text there, which is on 'a push-pull driver', not 'the push-pull driver'. But how does the rest not answer the question asked? – TonyM Sep 19 at 16:47
• you might have answered but i'm still trying to get some concepts right. Master is the one that starts the communication by setting the SDA low, yes? Where do you fit that part in this picture? I feel I am missing something – xyf Sep 19 at 18:33
• @xyf, ahh, I see, you don't understand the site. It's a Q&A site, not a 'one question leads to another' discussion forum nor an on-demand tutorial site. You ask a well-defined and specific question, having exhausted your research into all existing text you could possibly find on your subject, then people can volunteer their time to write specific answers to that... – TonyM Sep 20 at 8:57
• @xyf... Take the tour if you're in any way unclear on that. There is plenty - mountains - of pre-written text on bi-directional drivers, the I2C protocol and I2C implementations that you can refer to, all a Google search away. Naturally, this won't all be written again in an answer, only help bridging between what you've already taken the time to learn yourself and what's been asked. That's what we practice in professional engineering, after all. – TonyM Sep 20 at 8:57