I am reading this book "Computer Architecture and Organization" by Subrata Ghosal because I'm curious about how data is "stored" in the CPU register.

When I say "data is stored", I imagine something that allows me to:

  1. Write data to it
  2. As long as I don't rewrite, reading from it will return the last written data

And the book claims that the computer register allows that capability.

According to the book, a register can be made up of many clocked D flip flops, which are in turn can be made up of an S-R latch:

enter image description here

enter image description here

The D flip flop works like this:

  1. When CLK is 0, Q doesn't change
  2. When CLK is 1, D determines Q

Now a 4-bit register can be made up of 4 D flip flops:

enter image description here

I imagine this register is inside a RUNNING computer, then the CLK will alternate between 1 and 0 at specific interval. So my question involves this situation:

  • Supposed at point t0 in time: CLK is 1, I store in the third D flip flop the value 1 by setting the input to this flip flop to 1. Immediately after this, if I read from this flip flop, I will receive 1.
  • t1: CLK is 0: If I retrieve Q3, the value returned will be 1 -> I successfully retrieve the value I stored in this flip flop previously at t0.
  • t2: CLK is 1: Because now CLK is 1, Q3 will be depended on input of this flip flop. If at this point, the input is 1, then the value retrieved will be 0. But there's no guarantee that at this point, the input to this flip flop is 1. If the input is 0, I'll retrieve 0, which is not the value I previously stored at t0.

So it seems in order to retrieve the correct value I "stored" at a previous point in time, a necessary condition is that the correct input to the flip flop must also happen but there's nothing to guarantee that. This doesn't sound like "storing data" to me.

I must have misunderstood something but couldn't figure it out.

  • \$\begingroup\$ I think you are confusing the clock signal that drives the flip-flops with the overall system clock that runs the CPU. They are not the same clock. \$\endgroup\$
    – mike65535
    Commented Sep 21, 2020 at 12:42
  • 2
    \$\begingroup\$ @mike65535 actually they are the same clock. What is missing is the concept of an enable. \$\endgroup\$ Commented Sep 24, 2020 at 19:49

5 Answers 5


The circuit you show in Fig. 3.19 is (in my opinion) mislabeled as a D flip-flop. It is actually more clearly identified as a gated D-latch.

Gated D-latches are sometimes also confusingly labeled 'level-triggered flip-flops'. Again, better to use the term latch to be more clear.

Back to the diagram. The 'clock' would more correctly be called 'write' or 'enable'. You would not normally use a free-running clock to control a latch, but instead gate it with a write-enable signal.

Whatever you call it, the gated D-latch will hold its data as long as the 'clock' (really, enable) is held low, and follow the input while enable is held high, so at least that description is correct.

While D-latches or their equivalents (like SRAM cells) can be (and often are) used for storage, flops used for registers are typically of the ‘master-slave’ D-flip-flop type. That diagram looks like this: enter image description here

Simulate it here: Master-slave D flip-flop

Master-slave flops are sometimes called edge-triggered registers because they only change state on the clock edge. Master-slave flops are made up of two D-latch stages, with each stage gated on opposite clock phase.

For a positive-edge flop like the one shown above, the clock controls the stages as follows:

  • clock low: first stage open, second stage close
  • clock rise: Data transfers from first to second stage
  • clock high: first stage closed, second stage open (= held first stage)
  • clock fall: no action

In a system then, the main difference between a latch and a flop is this:

  • master-slave D flop timing is only referenced to one clock edge.
  • D latch timing also includes the latch-open time (clock high in your diagram).

This means that with the D flop, clock-to-Q is only related to the clock. This simplifies timing.

One more thing. You can construct D flip-flops from multiplexers. In CMOS this is the most common method. Here's an example: enter image description here

Simulate it here: Master-slave flop using muxes

Looking at it this way, you can see the follow-hold behavior of each latch more clearly.


The Trick is, a Register has some more signals and the FF is only a basic building block.

normally you have the data input, the data output, the clock input plus an enable signal. Data will only be transfered into the Register when enable is valid.

Of course you also can gate the clock like Marcus Müller said, but thats uncommon when you code logic for FPGA's or ASIC's.

Memory's or Registers for peripherals connected on a bus have more stuff like address decoders to generate the enable signals, etc...

so the plain D-FF is just a simplification to transport the basic concept. It's not how its done in reality. There are multiplexers, comparators and a lot other stuff around to get it work.

And while Register is synthesized logic, Memory is normally specialized IP with a dense layout to provide speed, low current consumption, low Area usage,...


I imagine this register is inside a RUNNING computer, then the CLK will alternate between 1 and 0 at specific interval.

The clock is only pulsed when writing data into the register. At all other times (including reading the register) the clock is inactive, so the data remains stored.

The data inputs can be connected to several registers as a bus. Only the register being clocked will have the data stored in it. The other registers will simply ignore the data and hold their contents.

To read data from a specific register onto the bus, its outputs must be connected through tri-state buffers or a multiplexer. Reading the register is then achieved by activating the buffer or selecting the appropriate input of the multiplexer. The register's clock is not pulsed when reading.

Here is part of the register board schematic in the C74-6502, a homemade reproduction of the 6502 CPU using TTL ICs:-

enter image description here

This design has separate Write and Read Data buses, each 8 bits wide (the blue lines in the schematic).

The 74AC238 and 74AC138 decode the register write and read lines respectively. The X and Y registers both use a 74AC574 Octal D flip/flop. Its Tri-state data outputs are enabled when the OC (/OE) input is low.

Here is the internal logic diagram of the 74AC574:-

enter image description here


then the CLK will alternate between 1 and 0 at specific interval.

no, that's the write clock. That only changes when there's valid data to store in the flip flop.

  • 2
    \$\begingroup\$ Not really true in a typical system. Typically the clock changes every cycle, but there's a distinct enable without which it is ignored. "Gating clocks" such that they actually stop is considered evil design practice and typically only found in slower old or peripheral contexts. \$\endgroup\$ Commented Sep 24, 2020 at 19:51

The pure flip-flop logic you have there updates on every clock cycle, which is not what you want.

In order to use these as a register, there is also a "write enable" signal that remains low unless the register is to be overwritten in this cycle.


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