In Razavi's Design of Analog CMOS Integrated Circuits (2nd edition), on page 65 he describes a way to derive the output resistance of a source-degenerated CS stage by inspection:
I understand how to derive this result from the small signal model but I don't understand the reasoning/intuition behind the inspection analysis.
He starts off by saying that if you apply a \$\Delta V\$ at the drain and measure the resulting \$ \Delta I\$, then all the \$ \Delta I \$ must pass through the degeneration resistor \$R_S\$. Sounds good, since the current has nowhere else to go.
He then derives a voltage divider equivalent circuit as shown in the linked image. However, he uses the result that the resistance looking into the source of a MOSFET is \$ \frac{1}{g_m+g_{mb}} \$ to insert a resistor in parallel with \$ R_S \$, which I don't understand. My confusion is that the resistance looking into the source of a MOSFET is derived when you have an ideal independent source applied at that terminal and calculate the voltage/current ratio (typical Thevenin resistance). How is that scenario applicable here? This analysis started off by saying that all of the \$ \Delta I\$ must pass through the resistor \$ R_S\$ but the model derived in figure 3.30(c) seems to imply that some of it is going through this other impedance.
(A side-doubt that I have is that here \$ \lambda \$ is not assumed to be zero since \$r_o\$ is finite but in then in this case resistance looking into the source shouldn't be exactly \$ \frac{1}{g_m+g_{mb}} \$, not sure if that makes a difference here.)