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I see that most FPGA vendors allow users to use an external clock signal as the feedback input to a PLL. When provided external feedback (which originates ultimately from the PLL output), the PLL will adjust its own output skew until the feedback input is aligned with that of the reference input.

Why would we possibly want to do this? I understand in the abstract, that instead of aligning the PLL output with the reference, we can align another point in the clock tree with the reference, but in what kind of design would this be useful?

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  • \$\begingroup\$ Imagine the FPGA generates a clock. The clock goes to the input of another chip. You want the other chip to see a particular clock phase. \$\endgroup\$
    – user253751
    Sep 21, 2020 at 12:43
  • \$\begingroup\$ I'm probably still missing something. In the case you described, we would connect the output of a PLL to the i/o pad. It's my understanding that, using the internal feedback on the PLL, which taps directly to the PLL output, is already as close as we can get to monitoring the phase of the clock leaving the chip. \$\endgroup\$ Sep 21, 2020 at 16:56
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    \$\begingroup\$ What if there's a long trace between the PLL output and the other chip? You could split it halfway (depending on the type of signal) and send one half back to the FPGA. You can probably think of more complicated scenarios too, like if you have some external clock divider, and you want to sync the output of that divider. \$\endgroup\$
    – user253751
    Sep 21, 2020 at 17:40

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you want the FPGA to align to the same clock as some other IC's... so you do not to resync inputs to a different clock. e.g a ethernet phy will align to each new frame it receives... and the MII Interface defines both clocks, Rx & Tx to be generated by the Phy. So an FPGA would need to sync to external clocks.

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