I have attempted to use a calculator without success.

Using a 5 V logic gate that will be driven by a Kinetis MCU, I would like to make a DAC. I have tried a 10k and 100nF filter but at 1 kHz I get a sawtooth on the output. I need <0.1V ripple at 500Hz.

Ideally I would like to lower the PWM frequency even more (say 200 Hz) but have a nice variable 0 - 5 V output. Any ideas on RC combo? Response is not that much of an issue. A full sweep from 0 V to 5 V in < 200 ms would be adequate.

PCBs are made so only option is to change the R/C values not redesign the layout.

Its currently logic TTL signal into a 10k then out of that to the "measure point" with a 100 nF cap to ground from there.

  • 1
    \$\begingroup\$ What ripple voltage can you tolerate on your smooth output? \$\endgroup\$
    – Andy aka
    Commented Sep 22, 2020 at 13:11
  • 3
    \$\begingroup\$ Why do you want a low PWM frequency? Usually you'd very much try to go higher. What's the advantage you're aiming for? "a full sweep < 200 ms" and 200 Hz really don't go together, even theoretically, unless you have very few bits of resolution. \$\endgroup\$ Commented Sep 22, 2020 at 13:12
  • \$\begingroup\$ Ideally <100mV ripple and low freeq due to MCU not getting bogged down (we are using SW timer) \$\endgroup\$
    – MattyT2017
    Commented Sep 22, 2020 at 13:13
  • 5
    \$\begingroup\$ @MattyT2017 then, don't use a software timer; the kinetis series has several PWM units, it feels unlikely you can't use one of them. But even so, Kinetis MCUs have >> 1 MHz clock frequency, what difference do 10 kHz vs 200 Hz really make to your application if you insist on doing this in software (still, don't.)? \$\endgroup\$ Commented Sep 22, 2020 at 13:14
  • 5
    \$\begingroup\$ again, sounds very much like you shouldn't do a software timer for this. Again, if you have 200 Hz PWM frequency, you're not getting anywhere close to 200 ms if you want to have anything smooth. And 20 channels in software doesn't sound like much work at all. I don't know your firmware architecture, but all that you describe hints at "took a wrong design turn somewhere". \$\endgroup\$ Commented Sep 22, 2020 at 13:21

2 Answers 2


Your requirements make things impossible.

Let's write things down. Ripple specs:

  • filter approach: single-stage RC low pass, these have 6 dB attenuation per octave
  • Voltage range \$U_{tot} = 5 \text{ V}\$
  • ripple \$U_{rip}< 0.1\text{ V} = \frac{U_{tot}}{50}\$ at 500 Hz, that's 13 dB suppression of the 5 V peak-to-peak you're putting into the filter
  • Therefore, you need at least roughly 13/6 octaves separation between PWM frequency and 500 Hz
  • Therefore, the cut-off frequency of the filter needs to be at least ca 1.1 kHz

You'll have to tell your software guy to rework his firmware, I'm afraid.

  • \$\begingroup\$ @ChrisStratton darn, you're right. \$\endgroup\$ Commented Sep 23, 2020 at 15:43

Just want to mention, TI used to have a nice Application Note for PWM DACs


Just replace the MSP430 PWM with what your µC provides...


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