I would like to control 48 outputs from a microcontroller, with individual access to each of them.

But let's focus on 16 outputs.

My initial solution involved a 1:16 demultiplexer and 16 (actually 8 dual) D-type Flip-Flops (DFFs). 4 pins would be used to set the address on the demux, 1 pin would be connected to the input of the demux and outputs would connected to the "clock" signal of the DFFs. Finally, one pin would be connected to the Data input of each DFF. That means in total 9 chips and 6 pins.

Thanks to a comment here a few days ago, I have now a new solution that involves 2x 8-bit addressable latches and a 1:2 demux i.e. 3 chips. I've looked for a 16-bit addressable latch but couldn't find one.

To control 48 outputs, I essentially triple the circuit, but also in the first case, I have 3 clock pins. So I can set the target address, set my "value" pin, then send a clock edge only to the right target.

Would anyone have a better option? Ideally, keeping direct access to any output. I'm having a look at things like shift registers though.

Anything I²C, SPI or any other bus is out of question.

Speed-wise, 100 Hz is the target (per output).

  • \$\begingroup\$ Have you considered mcp23017/mcp23s17 16-Bit I/O Expander with Serial Interface - microchip? ww1.microchip.com/downloads/en/devicedoc/20001952c.pdf \$\endgroup\$
    – tlfong01
    Commented Sep 23, 2020 at 4:57
  • \$\begingroup\$ I2C is your huckleberry if you can abide lower speeds. SPI is faster. \$\endgroup\$ Commented Sep 23, 2020 at 5:43
  • \$\begingroup\$ Sorry I knew I had forgotten to specify some things! \$\endgroup\$ Commented Sep 23, 2020 at 5:44
  • 3
    \$\begingroup\$ Why are serial buses out of the question? Your spec says that your product must be cumbersome and expensive? Also "I'm having a look at things like shift registers" contradicts "SPI or any other bus is out of question", since SPI is just a bunch of glorified shift registers. \$\endgroup\$
    – Lundin
    Commented Sep 23, 2020 at 6:23
  • 1
    \$\begingroup\$ If you are looking at shift registers, they also need serial comms compatible with SPI, so why all of a sudden you have requirement of no SPI, as that would basically rule out shift registers too. It makes no sense. For two GPIO pins you can implement software I2C and drive multiple IO expanders. For three GPIO pins, you can implement software SPI, and drive multiple IO expanders, or as many shift registers you like. Or perhaps a cheap MCU? \$\endgroup\$
    – Justme
    Commented Sep 23, 2020 at 7:50

2 Answers 2


Well, if you do not want any bus like I²C, SPI

and as little Pins as possible, simple shift registers are what you need. only two Pins needed at best. You just need to figure out which chips are in your voltage range and can be cascaseded.

e.g. Ti still offers a good range:


  • \$\begingroup\$ Do you know of any "shift register" that would update its output only once all bits have been pushed? Like by default for 8 bits, it outputs 8 zeroes, then after I push 8 new values (let's say only 1s), it transitions from 8x0 to 8x1. Or having an extra pin that would control that (3 pins, I push whatever I want, then transition that extra pin to update output)? \$\endgroup\$ Commented Sep 25, 2020 at 3:25
  • \$\begingroup\$ I found e.g. the assets.nexperia.com/documents/data-sheet/74LVC594A.pdf, but you need one more signal (when to transfer the shift reg to the outputs), so you need a further counter IC with overflow or 3 µC pins... You mabye found something better here en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits \$\endgroup\$
    – schnedan
    Commented Sep 25, 2020 at 10:04

In common case if you want to get more pins than aviable on you MCU you need some kind of serialization. In the extreme case it will be an SPI. Also it may be a quad-SPI or (if you use some more latches) something like octal-SPI.

But if the interaction logic between pins is raise simple you can use a tiny FPGA/CPLD to reduce required outputs of the MCU.

Take a look at FPGA/CPLD like MAX-10 / MachXO2 (5$-10$) or MAX-V (<2$).


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