Access type is basically a pointer in VHDL although perhaps it is not exactly the same thing as a pointer in C. I have found many examples online whereby we are using the VHDL access type to dynamically allocate memory to create a linked-list or some other type.
What I am looking for is, a way by which the VHDL access type can be made to point to a specific signal inside a tesbench so I can manipulate it but I might want to do the same for another variable also. This way a part of code will set the pointer to a specific signal and then I will change the value of this pointer to affect that specific signal. In this way, I don't need repeat of code that does the same thing to each of those signals.
VHDL does not have concept of returning an address of something which can be done in C language using the & operator.
Is this possible in VHDL-2008?