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Why is the ferrite bead isolation not recommended for any FPGA core voltages. When we usually refer any FPGA schematics the voltages output from regulators are directly connect to FPGA without any series isolation between regulator output and FPGA IC pins.

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  • \$\begingroup\$ Ferrite beads are very case specific. If not chosen correctly they make noise worse than if there were no bead at all. Also, why do you think an FPGA should a ferrite bead to begin with? What noise sensitive part are you expecting to find in an FPGA? It's not an analog component, for the most part. \$\endgroup\$ – DKNguyen Sep 25 at 5:47
  • \$\begingroup\$ Ferrite beads introduce an impedance peak at some high frequency. That's the last thing you want on an FPGA core supply. Look at all those capacitors on different pins in parallel to keep the impedance low. \$\endgroup\$ – Brian Drummond Sep 25 at 11:48
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This is mainly because to keep the voltage-drop from the transient current below the acceptable voltage noise threshold, the impedance of the PDN must be below a certain level, the target impedance. If you use the Ferrite bead there will be mismatch in the target impedance of the particular power rail of the FPGA.

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A choke in series with the supply rail is no silver bullet. If you use a choke as part of a filter, you'd better have a good idea how that filter behaves, as a whole :-) Try simulating the filter in Qucs/QucsStudio for a start, and be aware that the simulation will probably omit some painful real-world parasitic properties of the components and the PCB.

I've done some hands-on with LC filtering of power for a multi-stage RF amp cascade (a DIY noise generator, with several stages of SiGe amplification) and my initial designs have quickly explained to me that inductors and capacitors combined result in marvellous resonant peaks and nulls...

If I should understand your question in a broader context, you are asking about proper power blocking for fast digital chips. So in that context: be aware that even SMD ceramic capacitors have an inherent resonant frequency. And, when you combine several of them, you get anti-resonant behavior. You don't even need to add an explicit inductor of your own ;-) If you do need an inductor, you might want to consider throwing in some resistors too, to muffle the Q of the various resonant poles. There are special low-ESL capacitors specifically designed for power blocking. And, the fastest chips need to have some blocking in the package or on chip = any filter designed by you on the board around the chips can only do so much (some distance will always be left between your fastest ceramic cap and the package / chip). To learn more about the topic, I highly recommend an encyclopaedic appnote by Murata, numbered C39E - if I should recommend specific pages, check out page 24 in the file (20 in print) and for a complex view, read the whole chapter 8 starting on page 68 (64).

Also, for a basic idea what anti-resonance does, I'd recommend an online tool by Kemet, called the KSIM - unfortunately, for some reason, the recently introduced v3 of the KSIM doesn't allow me to select the "combined" curve of ESR+Inductance, which is where the anti-resonant peaking is supposed to emerge. The previous version of the tool used to show this nicely. This may be a problem with my particular browser brand and version.

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As with all engineering, a problem is observed and quantified and a commensurate solution implemented. The solution may be to do nothing or to do something. The latter has a cost, an effect on reliability and consequences from sourcing and obsolescence. So every part must earn its keep and be justified.

Inductors have performance characteristics that can be used to perform functions required by a circuit, once a requirement has been identified. Inductors can be used in power supply filter circuits to remove high frequency switching noise from reaching the load.

Inductors are sometimes wrongly regarded as 'magic frequency stoppers'. Inductors present a high impedance in response to a current change. A complex logic load like an FPGA draws high spike currents when its push-pull logic circuits transition, so when they demand current then the series inductor will obstruct it and the load voltage will fall, creating the noise they were there to magically stop. Although this can be counterbalanced by decoupling capacitors, it shows that inductors are to be used with care.

So, taking your question to the correct starting point: do FPGA supply rails require any additional filtering, such as by series ferrite beads?

No. FPGAs are a digital logic circuit. Their manufacturers nearly always specify minimum power supply decoupling capacitance, sufficient to reduce supply noise from typical switching supplies to suitable levels.

I imagine you have seen ferrite beads used in the supplies of PLLs within FPGAs. Those analogue circuits have particular requirements and these extra filters as a result. They prevent particularly high frequency switching noise from the PLLs reaching board supply rail tracks and planes and radiating EMI. So their requirements led to a circuit to solve a problem they would otherwise have.

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  • \$\begingroup\$ Ferrite beads are typically used in an LC circuit when placed on the power lines to avoid the problem you have outlined. However, we usually place them on the power supply end so that the noise is contained. If your ripple is too high, you may need to use a ferrite bead to decrease it. FPGAs have some tight voltage specifications. \$\endgroup\$ – user110971 Sep 25 at 6:44

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