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enter image description here

Wire the AND gate so that its (former) X input is driven by the counter’s Q1 output, and its (former) Y input is driven by the counter’s Q0 output. The output is still F. To ensure that you can see the values of the gate inputs in the simulator trace, connect counter’s Q1 output to your new output X, and its Q0 output to your new output Y.

I'm just confused on how to wire this up if the AND gate only has two inputs, and the counter has 4 outputs.

I also have to do this with an OR gate included with the AND gate, the one with an inverter (NOT gate), AND gate, and OR gate.

Any help would be appreciated as I'm super confused with this.

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    \$\begingroup\$ It sounds like the project says the two inputs to the AND gate are called x and y. The four outputs of the counter are Q0 Q1 Q2 Q3. It sounds like it wants you to connect only two of the counter outputs to the X and Y inputs, ignoring the other two (unconnected) counter outputs. Or, maybe I'm all wrong. \$\endgroup\$ – aMike Sep 25 '20 at 18:06
  • \$\begingroup\$ the way the assignment is worded makes me think that this assignment is a modification of a previous assignment .... go back to the previous assignment that had an AND gate with X and Y inputs and F output ... then follow this assignment's instructions step by step \$\endgroup\$ – jsotola Sep 26 '20 at 1:35
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The assignment is telling you to utilize two specific outputs of the counter; it does not tell you to do anything with the others.

It is also telling you to connect these two outputs to monitored nodes X and Y so that you can see what is going on. Presumably output F is also monitored.

In effect, the exercise at this stage only needs a two bit counter; maybe they only had a four bit counter model on hand, or maybe there's another step in this assignment or tomorrow's where a four bit counter will be needed. Given that this appears to be a hex counter which runs to a power of two before wrapping it doesn't really matter; if it were a decade or BCD counter, then the output pattern would be irregular.

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  • \$\begingroup\$ So in the next case where it wants an OR gate along with the AND gate, do I just connect Q2 and Q3 to the OR gate and to a different output? \$\endgroup\$ – Nicholas Taylor Sep 25 '20 at 18:23
  • \$\begingroup\$ If that's what that the assignment asks... \$\endgroup\$ – Chris Stratton Sep 25 '20 at 18:24
  • \$\begingroup\$ It doesn't specifically tell me what to connect. It is just a similar picture as originally provided, but includes an OR gate as well. \$\endgroup\$ – Nicholas Taylor Sep 25 '20 at 18:25
  • \$\begingroup\$ If it doesn't tell you what to connect, you cannot complete it. My assumption would be that you were supposed to do the exercise with an AND gate, and then replace it with an OR and so on, but that wouldn't make a ton of sense in the case of the NOT. Who knows. Time to utilize office hours? \$\endgroup\$ – Chris Stratton Sep 25 '20 at 18:27

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