# Is ECC feature in DDR realized with using Hamming code technique?

The fundamental formula for a Hamming coding is as below:

2^k≥n+k+1

Where k = # of parity bits and n = data bits

In a DDR system with ECC feature, every data byte will generate an additional ECC bit which makes a byte data 9 bits long.

However, if simply applying the Hamming code formula here, 8 bits of data will require 4 parity bits which will make the encoded data 12 bits long.

In this case, how can the DDR ECC feature be realized with the Hamming coding scheme?

• It's trivial to understand by using a venn diagram or a concept related to packing spheres, in this case.
– jonk
Sep 27, 2020 at 12:41

The ECC is not performed on an individual byte basis.

Usually, 8 bytes are combined with one parity bit per byte. Giving a total of 72 bits.

Since only 7 parity bits are needed to correct single-bit errors and 8 are available the extra bit can be used to detect double bit errors, although not correct the error.

Hamming code

• So every additional bit generated from a byte data is simply a parity result from that particular 8 bits data? Sep 27, 2020 at 13:06
• @Learner - no. The parity bits have to come from a combination of bits among multiple bytes. Sep 27, 2020 at 13:09
• Looking at the algorithm table from the Wikipedia, supposed 64 bits data only require 7 parity bits. Technically, can i say that the parity #8 in a DDR symbol is redundant? Sep 27, 2020 at 13:26
• @Learner - it adds the capability of detecting double-bit errors. Sep 27, 2020 at 19:43

DDR4 is not byte accessable. Each address has 64 bits or 8 bytes. The ECC makes each symbol 72 bits wide.

• that's mean the 2^k≥n+k+1 formula still valid for this? 2^8 >= 64+8+1 Sep 27, 2020 at 13:09
• @Learner No, 2^7 ≥ 64+7+1. When ECC is used for DDR RAM, there are usually a multiple of 9 chips (usually 9 chips with 8 bits per chip). Thus, there are 72 bits available: 64 bits for the data, 7 bits for the Hamming code and 1 bit which is often used as a parity bit to detect double bit errors. Sep 27, 2020 at 22:22

as far as I know, ECC with DDRam only can correct single bit errors.

• That's true for the usual SECDED scheme but there are others. Sep 27, 2020 at 13:03