In my circuit, I do not have control over what the power supply is used. Thus, I am preparing for the worst where a cheap noisy SMPS is used. I have some ADCs down the line that get their power from this so I don't want noise coupling to them.

Polling from different sources, I arrived at this circuit:


My approach is a choke + ferrite + RC filter. Would my approach be correct?

The choke I chose is this. I do not know if it's any good, though. I have chosen it primarily because it's small in size, and has 1k impedance which is fairly high (I have read that the higher impedance the better.)

For C5 and C6 as well I do not know how to calculate the values needed on those.

The reason for the ferrite is because of this paper same as choke I don't know what impedance value of the ferrite I should choose, I picked again a fairly high impedance value ferrite.

For the RC filter this is set to 3.3kHz low pass, although the components downstream uses 3.3V, I do not want to pull the voltage down too much.

Am I on the right track?

  • 1
    \$\begingroup\$ Drake I took the time to edit some of your questions for capitalization. In English the pronoun "I" is capitalized. \$\endgroup\$
    – JYelton
    Sep 28, 2020 at 17:15
  • \$\begingroup\$ Is the incoming power supply on the left exclusively used to power your circuit or can its raw 0 volt rail also be used with other equipment and that other equipment might make a different connection to your circuit. In other words, you haven't provided enough information. Also, on another matter, what are you doing about this question? I mean you can keep ignoring me but that doesn't seem sensible. \$\endgroup\$
    – Andy aka
    Sep 28, 2020 at 17:21

2 Answers 2


You are on the right track.

I'll offer an improvement on the LDO and on the Pre_LDO filtering, just to left of LDO.

  • LDO should be a high-speed LDO. There are LDOs with 1ua Iddq, and their high_frequency PSRR is very poor.

  • The Pre_LDO filtering (L + R + C) must attenuate the high frequency trash/spikes/ringing, so the ADC comparators have clean VDD.

  • if the ADC is to make 1 microvolt decisions, then you need to plan on attenuating the SwitchReg high frequency trash to 1uV.

  • remember the capacitors have ESR as a limit to low_frequency attenuation, and capacitors have ESL (1nanoHenry to 10nanoHenry, plus PCB Vias at 1nH) that cause a worsening of high frequency attenuation.

  • thus you may want LRC and LRC, before the LDOv ( that is two networks, each being 2_pole) to overcome the attenuation floor of capacitors (ESR and ESL)

  • you must design the GROUND; do not share vias between capacitors, since that lets the 2 capacitors become a resonant LC filter, and you get PEAKING

  • use a wide GROUND STRIP, or even a GROUND PLANE


Once you have designed and built a very_clean VDD, you must PROTECT IT from becoming polluted: Efields, Hfields, Ground Currents.

And magnetic shielding, such as standard thickness of copper foil --- 1.4 mils, 35 microns of the 1 ounce of copper per square foot, is

  • a few dB at 1MHz

  • a NEPER or 8.6dB at 4MHz

  • 3 NEPER or 26 dB at 40MHz

  • 10 NEPER or 86dB at 400MHz

but what about at 60Hertz powerline frequencies? ZERO

What about at the edge_speeds (10 microseconds?) of rectifier diode turn on and turn off frequencies? ZERO. Because is much slower than 1MHz.

Thus that CLEAN VDD will very vulnerable to adjacent power supplies.

How vulnerable?

We use a combined Biot_Savart and Faraday Law of Induction maths, like this

  • Vinduce = [ MU0 * MUr * Area / (2 * PI * Distance) ] * dI/dT

where we assume the loop (our rectangular region on the PCB) has Area, and that loop is coplanar with a Troublesome dI/dT from a long straight wire at Distance.

Substituting MU0 = 4 * PI * 1e-7 Henry/meter, and MUr = 1 (air, FR-4, copper) we get

  • Vinduce = [ 2e-7 * Area/Distance ] * dI/dT

Again, we want to compute a magnetic_field upset to our CLEAN_VDD. Any upset larger than 1 microvolt should be shielded against.

Now the assumptions: Distance = 1centimeter, Area = 1 centimeter by 1millimeter (this would be length of the PCB trace -- 1cm -- and height above the RETURN path for our CLEAN_VDD), and dI/dT (this is calculus derivative) of 1 ampere in 10 microSeconds as the power_supply diode current turns on at 60Hz (or 120Hz) rate.

  • Vinduce (remember, if > 1uV, its a problem)

  • Vinduce = [ 2e-7 Henry/meter * (1cm * 1mm) / 1cm ] * 1 amp/10 uSec

Now lets do the maths; notice everything is "1", so the maths is just powers of 10, and conversion factors

  • Vinduce = 2e-7 Henry/meter * 1mm * 1meter/1,000mm * 100,000 amp/second

  • Vinduce = 2e-7 * 1e-3 * 1e+5 = 2 * 10^(-7 -3 +5) = 2e-5 = 20 microVolts

Thus we have just computed, using our assumptions

  • 1cm between Power Supply and our CLEAN_VDD)

  • area of CLEAN_VDD trace (and its RETURN) is 1cm by 1mm height

  • turn on time of current thru rectifier diodes is 10 microsecond for 1 amp

That the deterministic trash induced, magnetically and at a SLOW edge of 10uS thus difficult to shield with thin copper foil (you will need steel), is


What to do? Shield it, with steel.

  • 2
    \$\begingroup\$ All of the above, except there's no reason not to use your own, known-quiet switcher in there someplace. Buck the 24V down to something comfortably above the necessary input voltage of the linear regulator, clean that, and then use a linear regulator. \$\endgroup\$
    – TimWescott
    Sep 28, 2020 at 21:33
  • \$\begingroup\$ @TimWescott That is a great idea, I could integrate a buck/boost thats outputs around 7v to give headrooom the LDO, with an added bonus now that my supply voltage can be as low as maybe 3.3v upto 24volts. Although nice Im hoping that it would not come to that, because i am unsure if i have enough space for it :/ \$\endgroup\$
    – DrakeJest
    Sep 29, 2020 at 2:26
  • \$\begingroup\$ What do you mean by "LRC and LRC" ? so there would be two of them ? \$\endgroup\$
    – DrakeJest
    Sep 29, 2020 at 2:26
  • \$\begingroup\$ You may find that a switching supply is smaller than the heat sink you'd need for an LDO dropping from 24V to 5 -- but that depends on the current you're pulling. And a switcher that you control can be made pretty quiet, and in ways that complement the following LDO. \$\endgroup\$
    – TimWescott
    Sep 29, 2020 at 3:44
  • \$\begingroup\$ Hello I have revisited the question to double check something and you have added more information thank you very much. \$\endgroup\$
    – DrakeJest
    Oct 6, 2020 at 19:11

For a clean output voltage, I would suggest you to use a "capacitor multiplier" before LDO in your circuit. According to my tests, it can reduce noise to a level of 15mVpp. It is basically used where ultra-low noise is desired like in Current sense Amplifier. Please watch this video to implement it in your application.

Best of Luck 👍🏻

enter image description here

  • \$\begingroup\$ I Saw this and tried simulating it but i could not get it to work See picture the output voltage dips to basically 0 . \$\endgroup\$
    – DrakeJest
    Oct 3, 2020 at 15:46
  • \$\begingroup\$ Thanks for the trial @DrakeJest, actually for 5V MOSFET will not work as the threshold voltage for MOSFET is higher. But the Transistor solution will work. You have to choose R3 register so that current through the transistor base =( Load Current)/(Beta of the transistor). in your case use 100ohm as R3 and 100uF C2 Capacitor. \$\endgroup\$
    – Deepak
    Oct 3, 2020 at 19:02

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