As the title suggests, I need to convert a 4-digit BCD number to binary.

I am aware of the doubble-dabble algorithm (https://en.wikipedia.org/wiki/Double_dabble), and that if you use it backwards you can convert from BCD to binary.

The algorithm works on paper but, as the title says, I need to do this on hardware using ICs from the 74LS family, and I can control them using a GAL22V10 by making my own state machine.

Below is an initial idea on how I would do it (this would be for only a 2 digit BCD number):

enter image description here

The problem here is that I dont know how I would subtract the 3 from the input digits without changing the number first into 2's complement and then back to binary and feed it into the register.

Would this be possible? Or is it more of a task for a microcontroller?


I dont know how I would subtract the 3 from the input digits without changing the number first into 2's complement and then back to binary and feed it into the register.

This isn't as complicated as you seem to fear. When you need to subtract 3, the number you're subtracting from is 8 or greater (i.e., always positive), and the result will obviously also be always positive. Therefore, you can simply use a 4-bit adder to add 11012 (the value -310 in 2's-complement) to the number and ignore the resulting carry bit.

1000 + 1101 = (1)0101
1001 + 1101 = (1)0110
1010 + 1101 = (1)0111
1011 + 1101 = (1)1000
1100 + 1101 = (1)1001
1101 + 1101 = (1)1010
1110 + 1101 = (1)1011
1111 + 1101 = (1)1100

Here's one idea for implementation. When the input number is >= 8 (i.e., the high bit is set), it adds -3; otherwise, it adds zero — passing the original value through.


simulate this circuit – Schematic created using CircuitLab

Interestingly, since you're converting a 4-digit BCD number, you could do it purely combinatorially using just 21 copies of the the above circuit and nothing else. It would get the job done in 10 × 16 ns (typ.) = 160 ns.

Or you could build a sequential circuit. It would require:

  • 2× 8-bit parallel-in, parallel-out register to hold the BCD data (74LS374)
  • 2× 8-bit serial-in, parallel-out shift register to hold the binary data (could use 74LS374 again)
  • 4× quad 2:1 mux to get the BCD data loaded into the registers (switching between loading and processing) (74LS157)
  • 3× the above circuit (74LS83)
  • your GAL sequencer

for a total of 12 chips. It would run at about 15 MHz max (again, using "typical" numbers) and require 16 clock cycles per conversion, for a total of 1.067 µs.

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Since you appear to be happy to user older technology, you could use a 16-bit xPROM (Flash EPROM or EEPROM if you prefer). Feed the BCD into the address lines and take the result from the bottom 10 bits of the data lines. The hex-file to program the PROM is left as an exercise for the reader.

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There are all sorts of ways. You can use two strings of counters. The first uses 4 74ls168s configured as a down-counter and the second uses 3 74ls161s, 74ls163s, or 74ls169s as an up-counter. A start pulse (properly synchronized to a clock feeding all 7 counters) loads the input into the first string, and zero into the second. Then the first counter chain downcounts while the second upcounts, and zero detection on a downcounting 168 is simple - which stops the counting and serves as a ready signal.

Of course, it will take as many as 10,000 cycles, but you have not provided any constraints on this.

Or you can use 3 74ls shift registers such as 74ls195 which feed an accumulator chain using (for instance) 3 74ls181s or 74ls283s feeding 3 more 74ls195s. A GAL converts a count code into the BCD values for decimal 1, 10, 100, and 1000 and loads them into the input shift registers, then shifts up and uses the original bit value within the digit to determine if addition takes place for a given BCD input.

This will only take about 4 shift register load cycles and 16 shift cycles.

I suspect that a GAL22V10 has sufficient resources to emulate a 74184, although I could be wrong. This would require 11 GALs, with a propagation time of about 6 or 7 worst-case GALs, but would not require any control timing at all, being entirely combinatorial.

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