I'm using a DP83867 Ethernet chip by Texas Instruments in an S-PQFP-G64, 10 x 10 mm package, the mechanical dimension and its recommended footprint are shown at the end of the question. As shown, the package includes a "4.44 x 4.44 mm" thermal pad, and the recommended stencil opening is "4.44 x 4.44 mm" as well. However, TI recommends an "8.0 x 8.0 mm" copper area on the PCB.

Unfortunately, the controller it's interfaced to has a mirrored pin order, a direct connection at the perimeter of the package is not possible without numerous undesirable vias and trace crossing. A more ideal routing is to fan the signals out via the bottom of the chip. but the "8.0 mm x 8.0 mm" copper area in the official footprint doesn't provide enough clearance. My solution was reducing the thermal pad to "7.0 x 7.0 mm", the extra 1 mm allowed me to route all signals within the design rules.

I have already received the PCB and assembled the board manually without any difficulty. After some minor debugging, the board is now fully functional.

Question: Is it an acceptable practice in PCB design? If I reduce the thermal pad size below what's in the official footprint, hypothetically (it's only a personal project and won't be manufactured), if I send this design for production, will it create any manufacturability problems in reflow soldering? In my opinion, there isn't anything obvious, downsizing the pad may reduce the soldering quality in a small QFN package, but in this case, the copper pad (7 x 7 mm) is still significantly greater than the thermal pad (4.44 x 4.44 mm) on the package. But I may have missed something.

BTW, increased thermal resistance is obvious, but let's assume it's negligible here.

Package Dimensions

Recommended Footprint

  • \$\begingroup\$ Make some worst case measurements of the pad's temperature and compare with datasheet ratings... \$\endgroup\$ Oct 1 '20 at 16:24
  • \$\begingroup\$ Could the pad size also be related to EMI? giving the chip an nice close ground plane? \$\endgroup\$
    – Aaron
    Oct 1 '20 at 16:27
  • \$\begingroup\$ @Aaron Interesting possibility. \$\endgroup\$ Oct 1 '20 at 16:32
  • \$\begingroup\$ @BrianDrummond What is the correct measurement technique to do that when you have an inaccessible pad? The best I can imagine is probing the top package temperature as a proxy, then using junction-to-case (top) thermal resistance to derive it... \$\endgroup\$ Oct 1 '20 at 16:35
  • \$\begingroup\$ That may be the best you can do. \$\endgroup\$ Oct 1 '20 at 17:11

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