# DC coupling - How can I reduce low frequency noise?

I'm using a precision 16-bit DAC (AD5689) to create DC bias current source, as indicated in the following picture and I'm detecting a high level of low frequency noise.

I represented L1 as an inductor for simplicity, but it is a filter with an high output inductance. Vout is a signal DC (controlled by the DAC) + AC (from L1).

At the moment I removed the AC component so that I could analyze the noise. I connected Vout to a opamp chain with gain of ~19k compensating the DC offset. From the datasheet of the DAC, the integrated noise (0.1 10Hz) is 6uV. That would give an output noise of 0.114V at this gain (without any filtering). I simulated the circuit with the opamp chain and I get 76mV of output integrated noise (0.1Hz 100MHz).

Scoping the output from the opamp chain, I got the following picture: (2V/div 1s/div)

I managed to track down the noise to Vout, since I probed the signals along the opamp chain and they are coherent. Given that the problem presents at low frequencies, I tried increasing C1 and C2 and adding a capacitor to the DAC output (300uF), but the noise level remained similar. I also resoldered the DAC just in case.

Is there a way to reduce this noise?

Eddit: Shorting Vout to ground reduces the noise level as seen in the following picture. Unfortunately I used a probe to short Vout which may have introduced some noise.

Eddit2:

Simulation of current and voltage requirements @ DAC , C1, C2

DAC: V(n006) I(v1)

C1: V(n001) I(C1)

C2: V(n002) I(C2)

• First, short VOUT to GND (disconnecting it from U1) and look at the noise of the opamp chain alone. If that's fine, then .... one observation : U1 In+ is derived from 2 supplies, of unknown noise, with no decoupling... Oct 1 '20 at 16:22
• Is the opamp U1 capable of driving that much capacitance even with 3Ω in series? Oct 1 '20 at 16:22
• @BrianDrummond I eddited the post to include the the output of the opamp chain with Vout connected to ground
– user264107
Oct 1 '20 at 17:23
• Looking at the datasheet I'd up it to at least 50Ω. Also, you may want to look at driving capacitive loads app notes. They usually put the feedback resistor on the other side of Rs. Oct 1 '20 at 18:36
• With 6 uV noise from the DAC, * 1.5 (U1 gain) * 19000 (opamp chain) how did you calculate 114mV? Did you omit U1 gain?Did you try decoupling U1 In+? How is the DAC voltage reference generated? (You could use the amp chain to probe these points) Oct 1 '20 at 18:37

As said in the comments and edit: Shorting $$\V_{out}\$$ to ground reduces noise.

Because the LTC6228/LTC6229 is designed for high bandwidth applications, the output has not been designed to drive capacitive loads directly. Load capacitance at the output creates a non-dominant pole in the open loop frequency response, worsening the phase margin. When driving capacitive loads, a resistor of 10Ω to 100Ω should be connected between the amplifier output and the capacitive load to avoid ringing or oscillation. The feedback should be taken directly from the amplifier output. Higher voltage gain configurations tend to have better capacitive drive capability than lower gain configurations due to lower closed loop bandwidth.

Choose at least 50 Ω. Also in the application notes: feedback resistor on the other side of $$\R_s\$$:

When feedback resistors are used to set up gain, care must be taken to ensure that the non-dominant pole formed by the feedback resistors and the parasitic capacitance at the inverting input does not degrade stability. For example if the amplifier is set up in a gain of +2 configuration with gain and feedback resistors of 1k, a parasitic capacitance of 7pF (device + PC board) at the amplifier’s inverting input will cause the part to oscillate, due to the pole formed at 45MHz. Adding a capacitor of 7pF across the feedback resistor as shown in Figure 2 will eliminate any ringing or oscillation. In general, if the resistive feedback network results in a pole whose frequency lies within the closed loop bandwidth of the amplifier, a capacitor can be added in parallel with the feedback resistor to introduce a zero whose frequency is close to the frequency of the pole, improving stability.

Last, decoupling/bypassing $$\U_1\$$ In+ with a a 680uF capacitor did improve.

For single supply applications, it is recommended that high quality 0.1µF||1000pF ceramic bypass capacitors be placed directly between each V+ pin and its closest V– pin with short connections. The V– pins (including the Exposed Pad) should be tied directly to a low impedance ground plane with minimal routing.

For dual (split) power supplies, it is recommended that additional high quality 0.1µF||1000pF [9.9e-10 = 0.99 nF] ceramic capacitors be used to bypass V+ pins to ground and V– pins to ground, again with minimal routing.