3
\$\begingroup\$

I am currently working on a flyback converter design based on the TI UCC28C42 multi-topology controller IC, and would like to simulate my circuit in LTSpice. I have created a small-signal averaged switch model in order to model the system's open-loop transfer function, and would like to run a transient simulation to verify that my compensator works as intended. To set up this transient simulation, I have imported an unencrypted PSpice model of the UCC28442 into LTSpice and built a flyback converter circuit around it. The circuit includes some idealizations like using a voltage-controlled switch instead of a MOSFET and a custom ideal transformer block in order to improve simulation speed. The transient simulation hangs around 700ns, when oscillations begin to appear on the UCC28C42's OUT port. I'm not sure if this is the source of the simulation freeze, but it seems to be an undesired behavior (the UCC28C42 is supposed to be switching on a much slower timescale--its RTCT timing cap hasn't even fully charged by 700ns).

I know that some PSPice models can have discontinuities that LTSpice doesn't like, and I'm hoping for some pointers on how to proceed. Are there any easy steps for sorting through the PSpice .subckt in the attached .LIB to make things more compatible with LTSpice? Should I give up and model the internals of the IC from scratch using discrete LTSpice elements? Thanks for taking a look!

Oscillation on OUT port

Full Circuit

The .LIB file:

* PSpice Model Editor - Version 16.0.0

*$
*****************************************************************************
** This product is designed as an aid for customers of Texas Instruments.  **
** No warranties, either expressed or implied, with respect to this third  **
** party software (if any) or with respect to its fitness for any          **
** particular purpose is claimed by Texas Instruments or the author. The   **
** software (if any) is provided solely on an "as is" basis. The entire    **
** risk as to its quality and performance is with the customer             **
*****************************************************************************
*
* This model was developed for Texas Instruments Incorporated by:
*   AEi Systems, LLC
*   5777 W. Century Blvd., Suite 876
*   Los Angeles, California  90045
*
* This model is subject to change without notice. Neither Texas Instruments Incorporated 
* nor AEi Systems is responsible for updating this model.
* For more information regarding modeling services, model libraries and simulation 
* products, please call AEi Systems at (310) 216-1144, or contact AEi Systems by email: 
* info@AENG.com. Or visit AEi Systems on the web at http://www.AENG.com.
*
*****************************************************************************
*
* (C) Copyright 2008 Texas Instruments Incorporated. All rights reserved.
* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
* Part: UCC28C42 (can be used for UCC38C42 also)
* Date: 11/05/2008
* Model Type: Transient Steady State
* Simulator: PSpice
* EVM Order Number: UCC38C44
* EVM Users Guide: slua274a, Oct 2008
* Datasheet: slus458d, Rev Jan 2007
*
*****************************************************************************
*
* Updates:
*
* Final 1.00
* Release to Web.
*
*****************************************************************************
.SUBCKT UCC28C42_STEADY  COMP   FB   CS   RTCT    GND    OUT   VDD   VREF  
****OSCILLATOR*****
STOF1 8 GND RTCT GND SOSC
GBDISCH RTCT GND Value = { IF ( V(8,GND) < 2.5 & V(13,GND) > 2.5, 8.4M, 0 ) }
RPULL 8 VREF 100K
****UVLO***********
STOF2 VDD 19 VDD GND SUVLO
RUVLO 19 GND 1MEG
RSTDBY VDD GND 309K ; startup current 
ROP 10 GND 2535 ; operating current
****REFERENCE*******
EBREF 13 GND Value = { IF ( V(19,GND) > 6, 5, 0 ) } 
RREG 10 VREF 0.158
CREF VREF GND 1N
V3 13 10 
***GB6 19 GND Value = { IF ( V(19,GND) > 7 , I(V3) , 0 ) }
GB6 19 GND Value = { IF (V(19,GND) > 4 , IF((I(V3)-I(EMY19))>2,
+ 2, IF((I(V3)-I(EMY19))<0, 0,(I(V3)-I(EMY19)))), 0 ) }
****CURRENT COMPARATOR*******
EB3 21 GND Value = { IF ( V(CS,GND) > V(16,GND), 5, 0 ) }
R7 CS GND 1MEG
RDELAY 21 22 1K
CDELAY 22 GND 200P
****ERROR AMPLIFIER**********
XAMP VREF FB COMP GND 28C4xAMP
****OFFSET LIMITER***********
R4 12 11 2MEG
R6 11 GND 1MEG
EB2 16 GND Value = { IF ( V(11,GND) > 1, 1, V(11,GND) ) }
V4 COMP 9 1
D1 9 12 D2
****OUTPUT DRIVER************
***XDRIVE 19 GND 5 OUT FETOUTC4X ; FETOUTC4X 2845OUT 
EMY19 191 GND VALUE = {V(19,GND)} 
XDRIVE 191 GND 5 OUT FETOUTC4X ; FETOUTC4X 2845OUT 
****S-R LATCH****************
XLATCH 8 VREF 22 GND 6 7 FFLOPC2
****OUTPUT AND GATE**********
EOut 5 GND Value = { IF ( V(VREF,GND) > 2.5 & V(7,GND) > 
+2.5 & V(8,GND) > 2.5, 5, 0 ) }
.MODEL SOSC VSWITCH (RON=.01 ROFF=1MEG VT=1.45 VH=0.95) ; VT=1.45 set to match 53k @ 3.3n/10k
.MODEL SUVLO VSWITCH (RON=.01 ROFF=10MEG VT=11.75 VH=2.75) 
.MODEL D2 D 
.ENDS UCC28C42_STEADY
*$
*****************************************************************************
** This product is designed as an aid for customers of Texas Instruments.  **
** No warranties, either expressed or implied, with respect to this third  **
** party software (if any) or with respect to its fitness for any          **
** particular purpose is claimed by Texas Instruments or the author. The   **
** software (if any) is provided solely on an "as is" basis. The entire    **
** risk as to its quality and performance is with the customer             **
*****************************************************************************
*
* This model was developed for Texas Instruments Incorporated by:
*   AEi Systems, LLC
*   5777 W. Century Blvd., Suite 876
*   Los Angeles, California  90045
*
* This model is subject to change without notice. Neither Texas Instruments Incorporated 
* nor AEi Systems is responsible for updating this model.
* For more information regarding modeling services, model libraries and simulation 
* products, please call AEi Systems at (310) 216-1144, or contact AEi Systems by email: 
* info@AENG.com. Or visit AEi Systems on the web at http://www.AENG.com.
*
*****************************************************************************
*
* (C) Copyright 2008 Texas Instruments Incorporated. All rights reserved.
* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
* Part: UCC28C42 (can be used for UCC38C42 also)
* Date: 11/05/2008
* Model Type: Transient Startup
* Simulator: PSpice
* EVM Order Number: UCC38C44
* EVM Users Guide: slua274a, Oct 2008
* Datasheet: slus458d, Rev Jan 2007
*
*****************************************************************************
*
* Updates:
*
* Final 1.00
* Release to Web.
*
*****************************************************************************
.SUBCKT UCC28C42_START  COMP   FB   CS   RTCT    GND    OUT   VDD   VREF  
****OSCILLATOR*****
STOF1 8 GND RTCT GND SOSC
GBDISCH RTCT GND Value = { IF ( V(8,GND) < 2.5 & V(13,GND) > 2.5, 8.4M, 0 ) }
RPULL 8 VREF 100K
****UVLO***********
STOF2 VDD 19 VDD GND SUVLO
RUVLO 19 GND 1MEG
RSTDBY VDD GND 309K ; startup current 
ROP 10 GND 2535 ; operating current
****REFERENCE*******
EBREF 13 GND Value = { IF ( V(19,GND) > 6, 5, 0 ) } 
RREG 10 VREF 0.158
CREF VREF GND 1N
V3 13 10 
***GB6 19 GND Value = { IF ( V(19,GND) > 7 , I(V3) , 0 ) }
GB6 19 GND Value = { IF (V(19,GND) > 7 , IF((I(V3)-I(EMY19))>100e-3,
+ 100e-3, IF((I(V3)-I(EMY19))<0, 0,(I(V3)-I(EMY19)))), 0 ) }
****CURRENT COMPARATOR*******
EB3 21 GND Value = { IF ( V(CS,GND) > V(16,GND), 5, 0 ) }
R7 CS GND 1MEG
RDELAY 21 22 1K
CDELAY 22 GND 200P
****ERROR AMPLIFIER**********
XAMP VREF FB COMP GND 28C4xAMP
****OFFSET LIMITER***********
R4 12 11 2MEG
R6 11 GND 1MEG
EB2 16 GND Value = { IF ( V(11,GND) > 1, 1, V(11,GND) ) }
V4 COMP 9 1
D1 9 12 D2
****OUTPUT DRIVER************
EMY19 191 GND VALUE = {V(19,GND)} 
***XDRIVE 19 GND 5 OUT FETOUTC4X ; FETOUTC4X 2845OUT 
XDRIVE 191 GND 5 OUT FETOUTC4X ; FETOUTC4X 2845OUT 
****S-R LATCH****************
XLATCH 8 VREF 22 GND 6 7 FFLOPC2
****OUTPUT AND GATE**********
EOut 5 GND Value = { IF ( V(VREF,GND) > 2.5 & V(7,GND) >
+ 2.5 & V(8,GND) > 2.5, 5, 0 ) }
.MODEL SOSC VSWITCH (RON=.01 ROFF=1MEG VT=1.45 VH=0.95) ; VT=1.45 set to match 53k @ 3.3n/10k
.MODEL SUVLO VSWITCH (RON=.01 ROFF=10MEG VT=11.75 VH=2.75) 
.MODEL D2 D 
.ENDS UCC28C42_START
*$
.SUBCKT 28C4xAMP  4     1    9   20
*                VREF  INV  OUT V-
R1 10 4 100K
R2 10 20 100K
R3 6 20 316MEG
C1 6 20 8.7p ; Bandwidth
E1 5 20 6 20 1
R4 1 20 50MEG ; Input Bias
I2 4 9 1m ; Isource
R6 20 3 300
Q1 20 13 9 QPMOD
I3 13 20 68U 
D14 3 13 DMOD
D15 20 6 DCLAMP
L1 2 3 10U
C2 3 20 200P
R9 5 2 5
C5 2 20 0.02U
G1 20 6 10 1 100U
.MODEL QPMOD PNP BF=217.647 ; sets the Isink current
.MODEL DCLAMP D (RS=10 BV=6.8 IBV=.01) 
.MODEL DMOD D
.ENDS 28C4xAMP
*$
.SUBCKT 2845OUT  4  7  3  12
*                +V -V IN OUT
I3 4 8 100U
D3 8 4 DMOD
D4 12 8 DMOD
Q3 8 1 9 QIN
Q4 12 9 7 QMOD
Q5 4 8 6 QMOD
I4 7 1 .9M
R1 3 2 10K
Q8 1 2 7 QIN
Q2 4 6 12 QMOD2
.MODEL QMOD NPN RC=1.5 RE=.5 RB=100 IKF=0.5 CJC=0.4P
.MODEL QMOD2 NPN TF=400P TR=400P
.MODEL QIN NPN BF=100 BR=2 IS=1E-16 VAF=50 
+ CJE=1.5P CJC=.15P TR=1N TF=4N
.MODEL DMOD D RS=1 IS=0.4U
.ENDS 2845OUT
*$
.SUBCKT FETOUTC4X  Vcc  Gnd In Out
*                  Vcc  -V  IN OUT
* simplify with b element with 5.5 ohms make it stiff vcc and zero
Rm1 Vcc Out 10MEG
M1 Vcc 3 Out Out _NMOS 
Rm2 Out Gnd 10MEG
M2 Gnd 3 Out Out _PMOS 
EB1 2 Out Value= { IF ( V(In,Gnd) > 2 , 5 , -5 ) }
R1 2 3 75
C2 3 Gnd 10p
C3 3 Vcc 10p
R2 3 Gnd 10Meg
.MODEL _NMOS NMOS KP=1 NSUB=1E9 RD=10 VTO=3
.MODEL _PMOS PMOS KP=1 RD=5.5 VTO=-3 NSUB=1E9
.ENDS FETOUTC4X
*$
.SUBCKT FFLOPC2 1  2 11 12 5  6
*              CLK D R  S  QB Q
X1 7 4 2 8 NAND3_0C2 
X2 8 3 10 9 NAND3_0C2 
X3 1 8 10 7 NAND3_1C2 
X4 4 9 1 10 NAND3_0C2 
X5 4 7 6 5 NAND3_1C2 
X6 5 10 3 6 NAND3_0C2 
X7 11 4 INV 
X8 12 3 INV 
.ENDS FFLOPC2
*$
.SUBCKT NAND3_0C2 1 2 3 4
E1 5 0 VALUE = { IF ( (V(1)>800M) & (V(2)>800M) & (V(3)>800M), 0, 5 ) }
R1 5 4 100
C1 4 0 20P IC=0
.ENDS NAND3_0C2 
*$
.SUBCKT NAND3_1C2 1 2 3 4
E1 5 0 VALUE = { IF ( (V(1)>800M) & (V(2)>800M) & (V(3)>800M), 0, 5 ) }
R1 5 4 100
C1 4 0 20P IC=3.5
.ENDS NAND3_1C2 
*$
.SUBCKT INV 1 2
E1 3 0 VALUE = { IF ( V(1)>800mV, 0, 5 ) }
R1 3 2 100
C1 2 0 10P IC=3.5
.ENDS INV
*$
*Diodes,Inc, Zener 10V-50V; 16.0V  1.00W   
.SUBCKT DI_SMAZ16  1   2
*     Terminals    A   K
D1 1 2 DF
DZ 3 1 DR
VZ 2 3 14.9
.MODEL DF D ( IS=25.7p RS=0.756 N=1.10
+ CJO=377p VJ=1.00 M=0.330 TT=50.1n )
.MODEL DR D ( IS=5.15f RS=0.460 N=1.49 )
.ENDS DI_SMAZ16  
*$
.SUBCKT FQB6N80   10 20 30
*     TERMINALS:  D  G  S
M1   1  2  3  3  DMOS L=1U W=1U
RD  10  1  0.711
RS  40  3  38.5m
RG  20  2  42.7
CGS  2  3  1.14n
EGD 12  0  2  1  1
VFB 14  0  0
FFB  2  1  VFB  1
CGD 13 14  180p
R1  13  0  1.00
D1  12 13  DLIM
DDG 15 14  DCGD
R2  12 15  1.00
D2  15  0  DLIM
DSD  3 10  DSUB
LS  30 40  7.50n
.MODEL DMOS  NMOS(LEVEL=1 LAMBDA=2.00m VTO=4.00 KP=8.40
.MODEL DCGD D (CJO=180p VJ=0.600 M=0.680
.MODEL DSUB D (IS=24.1n N=1.50 RS=77.6m BV=800
+ CJO=477p VJ=0.800 M=0.420 TT=650n
.MODEL DLIM D (IS=100U)
.ENDS FQB6N80
*$
.model D1N4148  D(Is=2.682n N=1.836 Rs=.5664 Ikf=44.17m Xti=3 Eg=1.11 Cjo=4p
+ M=.3333 Vj=.5 Fc=.5 Isr=1.565n Nr=2 Bv=100 Ibv=100u Tt=11.54n)
*$
.SUBCKT C94SA476X0020 2 4
R1 2 3 38.106M
C1 3 1 46.980U IC = 12
R3 5 4 150
R2 2 4 21.285MEG
R4 3 26 4.7633G
R6 3 7 4.7633K
C5 7 1 18.792U IC = 12
R7 3 10 47.633 
C6 10 1 18.792U IC = 12
R8 3 13 476.33M
C7 13 1 18.792U IC = 12
C2 26 1 18.792U IC = 12
R9 3 28 47.633MEG
C3 28 1 18.792U IC = 12
R10 3 29 476.33K
C4 29 1 18.792U IC = 12
L8 1 5 2.0000N
R24 1 5 114.32M
L12 5 4 10.0000N
.ENDS C94SA476X0020
*$
.SUBCKT FLYBACK_UCC28C4x 1   7   5  4  6 PARAMS: L=12u NC=100 NP=1 RB=6.8 F=190k EFF=1 TS=300n
*               VIN RTN VC VOUT D
*Used for voltage or current mode buck & buck-boost converters.
*{L} primary inductance in Henries
*{NC} current transformer turns ratio
*{NP} Power transformer turns ratio
*{F} switching frequency in Hz
*{EFF} efficiency
*{RB} current transformer burden resistor in ohms
*{TS} propagation delay time in the current loop
*
*B1 IS INPUT CURRENT
GB1 1 7 Value={ V(4)*I(VM1)/(EFF*V(1)) }
*B2 IS PEAK INDUCTOR CURRENT
EB2 2 7 Value={ IF ( V(5) > 0 , (V(5)*NC/(RB))+(V(1)*TS/L) , 0 ) }
*B3 IS MINIMUM INDUCTOR CURRENT
EB3 3 7 Value={ IF ( V(2)-(1/NP*V(4)/(L*F*(1+(1/NP*V(4)/V(1))))) > 0 , V(2)-(1/NP*V(4)/(L*F*(1+(1/NP*V(4)/V(1))))) , 0 ) }
*B4 IS OUTPUT CURRENT
GB4 7 8 Value={ L*F*EFF*(V(2)^2-V(3)^2)/(2*V(4)) }
*B5 IS DUTY CYCLE
EB5 6 7 Value={ IF ( L*F*(V(2)-V(3))/V(1) < 1 , L*F*(V(2)-V(3))/V(1) , 1 ) }
VM1 8 4
.ENDS FLYBACK_UCC28C4x 
*$
.SUBCKT XFMR 1 2 3 4 PARAMS: RATIO=1
* SINGLE WINDING TRANSFORMER 
Rpar 1 2 1MEG
Ea 5 4 VALUE = { V(1,2)*RATIO }
Ga 1 2 VALUE = { I(VMa)*RATIO }
Rser 6 3 1U
VMa 5 6 
RP2 5 0 100Meg
RP3 6 0 100Meg
.ENDS XFMR
*$
.SUBCKT MOC8101 1 2 3   5
* ISOLATOR      A C COL EMITTER
RB 4 0 100Meg
VM 1 6
D1 6 2 LED
H1 7 0 VM .0055
R1 7 8 1K
C1 8 0 3.35nF
G1 3 4 8 0 1
Q1 3 4 5 MPSA06
.MODEL LED D(N=1.7 RS=.7 CJO=23.9P IS=85.3p BV=6 IBV=10U 
+ VJ=0.75 M=0.333 TT=4.32U)
.MODEL MPSA06 NPN (IS=15.2F NF=1 BF=589 VAF=98.6 IKF=90M ISE=3.34P NE=2 
+ BR=4 NR=1 VAR=16 IKR=0.135 RE=0.343 RB=1.37 RC=0.137 XTB=1.5
+ CJE=9.67P VJE=1.1 MJE=0.5 CJC=7.34P VJC=0.3 MJC=0.3 TF=10.29n TR=276N)
.ENDS MOC8101
*$
.SUBCKT XFMRAUX 1    2    3     4     10    11  PARAMS: RATIO_POW=1 RATIO_AUX=1
*Connections     +Pri -Pri +SecP -SecP +SecA -SecA
*Parameters:
* Ratio = Secondary/Primary turns ratio
*
*  1_______   _______3
*    +     ) (          A VsPower
*          ) (_______4   
*    VPrim )  _______10
*          ) (
*    -     ) (          B VsAux
*  2_______) (_______11
*
*  RATIO_POW = 1:A
*  RATIO_AUX = 1:B
*
Rpri 1 2 1MEG
E1 5 4 Value={RATIO_POW*V(1,2)}
G1 1 2 Value={RATIO_POW*I(Vvs)}
Ra 6 3 1U
Vvs 5 6
E2 20 11 Value={RATIO_AUX*V(2,1)}
G2 2 1 Value={RATIO_AUX*I(Vaux)}
Rb2 21 10 1U
Vaux 20 21 
.ENDS XFMRAUX
*$
.SUBCKT MTD1N60E  100 20 30
*     TERMINALS:  D  G  S
LDRAIN  100  10  4.5e-09
M1   1  2  3  3  DMOS L=1U W=1U
RD  10  1  2.80
RS  40  3  0.148
RG  20  2  150
CGS  2  3  218p
EGD 12  0  2  1  1
VFB 14  0  0
FFB  2  1  VFB  1
CGD 13 14  77.0p
R1  13  0  1.00
D1  12 13  DLIM
DDG 15 14  DCGD
R2  12 15  1.00
D2  15  0  DLIM
DSD  3 10  DSUB
LS  30 40  7.50n
.MODEL DMOS  NMOS(LEVEL=1 LAMBDA=2.00m VTO=3.30 KP=0.896
.MODEL DCGD D (CJO=77.0p VJ=0.600 M=0.680
.MODEL DSUB D (IS=4.15n N=1.50 RS=70.0m BV=635
+ CJO=120.3p VJ=0.800 M=0.420 TT=464n
.MODEL DLIM D (IS=100U)
.ENDS MTD1N60E
*$
.MODEL SSR8045 D IS=9.3983E-6 N=1.9085 RS=4.8543E-3
+ CJO=2.8578E-9 M=.3333 VJ=.75
+ ISR=175.46E-6 BV=44.928 IBV=12.938E-3 TT=1.4427E-12
*$
*Diodes,Inc.
.MODEL DI_S1K D ( IS=7.31e-018 
+ RS=42.0m BV=800 IBV=5.00u CJO=42.4p  
+ M=0.333 N=0.775 TT=4.32u) 
*$
* Diodes, Inc.
.MODEL ES3B D (IS=7.27p RS=22.4m BV=100 IBV=10.0u
+ CJO=83.2p  M=0.333 N=0.700 TT=36.0n )
*$
.model MUR160   D(Is=1.043p Rs=74.44m Ikf=2.705m N=1 Xti=2 Eg=1.11 Cjo=28.43p
+       M=.6225 Vj=.75 Fc=.5 Isr=7.011n Nr=2 Tt=123.3n)
*$
.model MBR140P  D(Is=2.835u Rs=47.12m Ikf=.3227 N=1 Xti=0 Eg=1.11 Cjo=302.5p
+       M=.7206 Vj=.75 Fc=.5 Isr=16.98u Nr=2)
*$

Transformer file:

Version 4
SHEET 1 1128 680
WIRE -32 208 -128 208
WIRE 320 208 176 208
WIRE -32 240 -32 208
WIRE 176 240 176 208
WIRE -32 352 -32 320
WIRE -32 352 -128 352
WIRE 176 352 176 320
WIRE 320 352 176 352
FLAG -128 208 IN_P
IOPIN -128 208 In
FLAG -128 352 IN_M
IOPIN -128 352 In
FLAG 320 208 OUT_P
IOPIN 320 208 Out
FLAG 320 352 OUT_M
IOPIN 320 352 Out
SYMBOL bv 176 224 R0
WINDOW 3 54 85 Left 2
SYMATTR Value V=(V(IN_P) - V(IN_M)) * {N}
SYMATTR InstName BVOUT
SYMBOL bi -32 240 R0
SYMATTR InstName BIN
SYMATTR Value I=-I(BVOUT)*N
TEXT 16 424 Left 2 !.PARAM N=1

Transformer Symbol (not the prettiest):

Version 4
SymbolType BLOCK
RECTANGLE Normal -80 -32 96 32
WINDOW 0 -80 -48 Left 2
PIN -80 -16 LEFT 8
PINATTR PinName IN_P
PINATTR SpiceOrder 1
PIN -80 16 LEFT 8
PINATTR PinName IN_M
PINATTR SpiceOrder 2
PIN 96 -16 RIGHT 8
PINATTR PinName OUT_P
PINATTR SpiceOrder 3
PIN 96 16 RIGHT 8
PINATTR PinName OUT_M
PINATTR SpiceOrder 4

The circuit:

Version 4
SHEET 1 1884 1108
WIRE 1680 -160 1616 -160
WIRE 1680 -128 1680 -160
WIRE 1040 -96 720 -96
WIRE 1120 -96 1040 -96
WIRE 1504 -96 1344 -96
WIRE 1616 -96 1616 -160
WIRE 1616 -96 1504 -96
WIRE 720 -64 720 -96
WIRE 1040 -64 1040 -96
WIRE 1504 -64 1504 -96
WIRE 1616 -64 1616 -96
WIRE 1120 -48 1120 -96
WIRE 1136 -48 1120 -48
WIRE 1344 -48 1344 -96
WIRE 1344 -48 1312 -48
WIRE 1136 -16 1120 -16
WIRE 1344 -16 1312 -16
WIRE 1040 48 1040 16
WIRE 1120 48 1120 -16
WIRE 1120 48 1040 48
WIRE 1344 48 1344 -16
WIRE 1376 48 1344 48
WIRE 1504 48 1504 0
WIRE 1504 48 1440 48
WIRE 1616 48 1616 16
WIRE 1616 48 1504 48
WIRE 720 64 720 16
WIRE 1040 112 1040 48
WIRE 336 128 256 128
WIRE 416 128 336 128
WIRE 864 128 720 128
WIRE 992 128 944 128
WIRE 336 144 336 128
WIRE 256 160 256 128
WIRE 992 176 976 176
WIRE 416 208 416 128
WIRE 448 208 416 208
WIRE 640 208 640 176
WIRE 640 208 608 208
WIRE 976 208 976 176
WIRE -368 240 -368 208
WIRE -32 240 -96 240
WIRE 256 240 256 224
WIRE 256 240 -32 240
WIRE 336 240 336 224
WIRE 336 240 256 240
WIRE 448 240 336 240
WIRE 720 240 720 128
WIRE 720 240 608 240
WIRE -96 256 -96 240
WIRE 448 272 128 272
WIRE 832 272 608 272
WIRE 896 272 832 272
WIRE 1040 272 1040 192
WIRE 1040 272 976 272
WIRE 128 288 128 272
WIRE 448 304 336 304
WIRE 656 304 608 304
WIRE 832 304 832 272
WIRE 1040 304 1040 272
WIRE -368 352 -368 320
WIRE -96 352 -96 336
WIRE 656 368 656 304
WIRE 128 400 128 368
WIRE 336 400 336 304
WIRE 336 400 128 400
WIRE 832 400 832 368
WIRE 1040 400 1040 384
WIRE 128 416 128 400
WIRE 128 496 128 480
FLAG -368 352 0
FLAG -368 208 12v
FLAG 640 176 12v
FLAG 656 368 0
FLAG 976 208 0
FLAG 128 496 0
FLAG 720 64 0
FLAG 1680 -128 0
FLAG 1616 48 v
FLAG -96 352 0
FLAG -32 240 v_err
FLAG 1040 400 0
FLAG 832 400 0
SYMBOL voltage 720 -80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR InstName Vg
SYMATTR Value {V_g}
SYMBOL voltage -368 224 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL sw 1040 208 M180
SYMATTR InstName S1
SYMATTR Value SW_ideal
SYMBOL res 1024 288 R0
SYMATTR InstName R1
SYMATTR Value 0.75
SYMBOL cap 240 160 R0
SYMATTR InstName C1
SYMATTR Value 10k
SYMBOL res 320 128 R0
SYMATTR InstName R2
SYMATTR Value 10n
SYMBOL res 112 272 R0
SYMATTR InstName R3
SYMATTR Value 15.4k
SYMBOL cap 112 416 R0
SYMATTR InstName C2
SYMATTR Value 1000p
SYMBOL transformer 1216 -32 R0
WINDOW 39 -27 -65 Left 2
SYMATTR SpiceLine n={1/n}
SYMATTR InstName X1
SYMBOL ind 1024 -80 R0
SYMATTR InstName L1
SYMATTR Value 1.5m
SYMBOL diode 1376 64 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value D_ideal
SYMBOL cap 1488 -64 R0
SYMATTR InstName C3
SYMATTR Value 2200µ
SYMBOL res 1600 -80 R0
SYMATTR InstName R4
SYMATTR Value {R}
SYMBOL bv -96 240 R0
WINDOW 3 -82 -53 Left 2
SYMATTR Value V=({V_o}-V(v))/10
SYMATTR InstName B1
SYMBOL res 960 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 100
SYMBOL res 992 256 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 3.8k
SYMBOL cap 816 304 R0
SYMATTR InstName C4
SYMATTR Value 100p
SYMBOL AutoGenerated\\UCC28C42_START 528 256 R0
SYMATTR InstName U1
TEXT 752 -208 Left 2 !;ac dec 1e3 1e-3 1G
TEXT 144 -152 Left 2 !.param V_g=120 V_o=24 P_o=40 n=5 D=0.5 D_p=1-D I_c=P_o/V_o*n*D R=V_o*V_o/P_o L=100u
TEXT 752 -264 Left 2 !.tran 0 20m 0m uic
TEXT 424 -336 Left 2 !.options abstol 1u
TEXT 1248 -416 Left 2 !.model SW_ideal SW(Roff=1G Ron=1u Von=1 Vh=0.1)\n.model D_ideal D(Roff=1G Ron=1m)

```
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  • 1
    \$\begingroup\$ I think concernedcitizen (something like that) will have more to say. But in general I know that you should prefer current sources to voltage sources where possible and probably only use a level 2 switch, if you use one at all (it's smooth instead of abrupt.) \$\endgroup\$ – jonk Oct 1 '20 at 23:14
2
\$\begingroup\$

TINA seems to use allow the use of GND as a generic label, but in LTspice that is the global zero, 0. With care, it can be adjusted. Another thing is the models that are translated from TINA are usually a behavioural nightmare, and this one is no exception: it's full of ill-conditioned logical expressions assigned to stiff voltage sources. It may work in TINA, but that's, most probably, because it has a different engine under the hood.

You forgot the contents of the symbol for the IC, but that's a minor inconvenience since it looks like it's auto-generated. That's what I did, too, even if some pins needed replacing.

Looking over the schematic, B1 is used wrong here. The node labeled v_err is supposed to come from either a resistive divider at the output, or some galvanically isolated error amplifier (TL431 with optocoupler is very common in flybacks, or similar). So even the expression you used in B1 is wrong, because that is meant to be the function of the built-in error amplifier inside the UCC.

Also, the feedback network, R1 and C2, not only have reversed values, but they should not be in parallel unless the feedback came from an isolated error amplifier, which, if B1 was meant to be that one, then it's not enough to have a simple difference (and gain adjustment) -- it needs proper pole-zero fedback.

There are a few other details about the way the schematic is built: R5 is useless since the control input of the VCSW is voltage mode (i.e. no current), and if you're going to use a transformer, then either use an ideal one (the one you have), or use two coupled inductors for proper inductive loading; what you did is sometimes used for nonlinear transformers, in case L1 was nonlinear. Then the .model cards for the diode and the switch could use a bit of tuning. As jonk mentions, level=2 for the VCSW works best, but you can use the level=1 (if not specified, it defaults to it) but with a negative hysteresis, vh, which will force a low order polynomial smooth transition. For the diode, epsilon and revepsilon are the equivalent of negative vh for the VCSW: they set a small quadratic knee region.

That said, I tried a lot of tricks to try to make the schematic work, but I had no luck. In fact, even if I managed to make it run for a few microseconds, it failed when I tried to replace the VCSW with an NMOS. So, looking in the datasheet, it looks like this UCC is a better version of the x84x series, which is a classic current-mode controller.

With this in mind, and seeing that you're more likely to want to see how this works, rather than will this work, you can either use some already existent models for x84x that work in LTspice (if you can tolerate the lesser values for frequency, rise/fall times, etc, compared to this one), or simply make your own circuit which requires a lot less components and will work. Here is an attempt that doesn't make use of threshold detection and other minor choices that the UCC has, and simply uses an exploded model of a current-mode control for a flyback. It doesn't try to accurately model the UCC, but it works in an equivalent way. Please note that I have no idea what your requirements are and I simply re-used whatever values I found in your schematic. This is the result:

test

There is no oscillator since all that's needed here is the SET pulse, and the switching frequency can be set through the f parameter, and the maximum pulse width through a. I used a lower value for the output cap to avoid waiting for too long, and I re-arranged the feedback network to be series RC (proper PI). Whatever your requirements are, adjust as needed, you're the one who should know better what you want. If you need finer control for the NMOS driver, add a totem-pole made with VCSW

And here is the contents of the .asc file, it doesn't need any external libraries:

Version 4
SHEET 1 1856 680
WIRE 144 -304 80 -304
WIRE 160 -304 144 -304
WIRE 368 -304 304 -304
WIRE 432 -304 368 -304
WIRE 560 -304 496 -304
WIRE 864 -304 800 -304
WIRE 1072 -304 864 -304
WIRE 1360 -304 1296 -304
WIRE 1504 -304 1424 -304
WIRE 1568 -304 1504 -304
WIRE 1616 -304 1568 -304
WIRE 1680 -304 1616 -304
WIRE 1792 -304 1760 -304
WIRE 1824 -304 1792 -304
WIRE 1840 -304 1824 -304
WIRE 80 -272 80 -304
WIRE 304 -272 304 -304
WIRE 800 -272 800 -304
WIRE 1296 -272 1296 -304
WIRE 1072 -256 1072 -304
WIRE 1504 -256 1504 -304
WIRE 1616 -256 1616 -304
WIRE 1792 -240 1792 -304
WIRE 1296 -144 1296 -192
WIRE 1504 -144 1504 -192
WIRE 1504 -144 1296 -144
WIRE 1616 -144 1616 -176
WIRE 1616 -144 1504 -144
WIRE 1792 -144 1792 -160
WIRE 1792 -144 1616 -144
WIRE 1072 -112 1072 -176
WIRE 1504 -112 1504 -144
WIRE 128 -80 64 -80
WIRE 272 -80 192 -80
WIRE 832 -32 640 -32
WIRE 1024 -32 896 -32
WIRE 832 0 784 0
WIRE 384 16 352 16
WIRE 544 16 448 16
WIRE 1072 16 1072 -16
WIRE 1152 16 1072 16
WIRE 1296 16 1232 16
WIRE 1344 16 1296 16
WIRE 64 32 64 -80
WIRE 64 32 16 32
WIRE 112 32 64 32
WIRE 272 48 272 -80
WIRE 272 48 192 48
WIRE 384 48 272 48
WIRE 1072 48 1072 16
WIRE 112 64 16 64
WIRE 1296 64 1296 16
WIRE 1072 144 1072 128
WIRE 1296 144 1296 128
FLAG 800 -192 0
FLAG 864 -304 V+
FLAG 80 -192 0
FLAG 144 -304 2.5V
FLAG 16 64 2.5V
FLAG 304 -192 0
FLAG 368 -304 blank
FLAG 784 0 blank
FLAG 1072 144 0
FLAG 1296 144 0
FLAG 16 32 ref
FLAG 1504 -112 0
FLAG 1824 -304 ref
FLAG 1344 16 cs
FLAG 352 16 cs
FLAG 560 -304 _blank
FLAG 544 -32 _blank
FLAG 1568 -304 out
SYMBOL SpecialFunctions\\ota 144 -16 R0
WINDOW 3 -47 114 Left 2
WINDOW 123 -47 136 Left 2
WINDOW 39 -47 158 Left 2
SYMATTR InstName Aea
SYMATTR Value rout=1 cout=8m
SYMATTR Value2 vhigh=10 vlow=-10
SYMATTR SpiceLine iout=1
SYMBOL voltage 800 -288 R0
SYMATTR InstName V2
SYMATTR Value 120
SYMBOL cap 192 -96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10n Rser=10k
SYMBOL voltage 80 -288 R0
SYMATTR InstName V3
SYMATTR Value 2.5
SYMBOL Digital\\diffschmitt 384 -32 R0
WINDOW 3 -28 113 Left 2
SYMATTR InstName A1
SYMATTR Value vt=0 vh=0 tau=10n tripdt=10n
SYMBOL voltage 304 -288 R0
SYMATTR InstName V4
SYMATTR Value pulse 0 1 0 10n 10n {a/f} {1/f}
SYMBOL Digital\\srflop 592 -80 R0
WINDOW 3 -62 -22 Left 2
SYMATTR InstName A2
SYMATTR Value tau=10n tripdt=10n
SYMBOL res 1056 32 R0
SYMATTR InstName R1
SYMATTR Value 0.75
SYMBOL res 1248 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 3.8k
SYMBOL cap 1280 64 R0
SYMATTR InstName C2
SYMATTR Value 100p
SYMBOL ind2 1056 -272 R0
WINDOW 123 36 107 Left 2
WINDOW 39 36 130 Left 2
SYMATTR InstName L1
SYMATTR Value 1.5m
SYMATTR Type ind
SYMATTR Value2 Rser=10m
SYMATTR SpiceLine Rpar=50k
SYMBOL ind2 1312 -176 R180
WINDOW 123 36 107 Left 2
WINDOW 39 36 130 Left 2
SYMATTR InstName L2
SYMATTR Value {1.5m/25}
SYMATTR Type ind
SYMATTR Value2 Rser=1m
SYMATTR SpiceLine Rpar=10k
SYMBOL diode 1360 -320 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMBOL cap 1488 -256 R0
WINDOW 123 24 84 Left 2
SYMATTR InstName C3
SYMATTR Value 1m
SYMATTR Value2 Rser=25m
SYMBOL res 1600 -272 R0
SYMATTR InstName R3
SYMATTR Value 14.4
SYMBOL res 1664 -288 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 9k
SYMBOL res 1776 -256 R0
SYMATTR InstName R5
SYMATTR Value 1k
SYMBOL Digital\\inv 432 -368 R0
WINDOW 3 -5 97 Left 2
SYMATTR InstName A4
SYMATTR Value tau=10n tripdt=10n
SYMBOL Digital\\and 864 -80 R0
WINDOW 3 -68 114 Left 2
WINDOW 123 -68 136 Left 2
WINDOW 39 -68 158 Left 2
SYMATTR InstName A3
SYMATTR Value tau=10n tripdt=10n
SYMATTR Value2 vlow=0.2 vhigh=11.8
SYMATTR SpiceLine ref=0.5 rout=10
SYMBOL nmos 1024 -112 R0
SYMATTR InstName M1
SYMATTR Value BSC600N25NS3
TEXT 32 -536 Left 2 !.parma f=100k a=0.95
TEXT 992 -328 Left 2 !k l1 l2 1
TEXT 24 -488 Left 2 !.model sw sw ron=0.1 roff=0.1g vt=0.5 vh=-0.5\n.model d d ron=50m roff=50meg vfwd=0.45 vrev=1k epsilon=0.1 revepsilon=50m
TEXT 32 -400 Left 2 !.tran 50m uic
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  • 1
    \$\begingroup\$ Thank you so much! This was incredibly helpful. \$\endgroup\$ – CoolNamesAllTaken Oct 2 '20 at 22:16
  • 1
    \$\begingroup\$ I fixed the mistakes you mentioned and replicated your transient schematic (I had taken a crack at replicating the guts of the IC earlier but was missing a few key pieces). Things look like they're working great. I'm still using an ideal switch and the ideal transformer, and the sim completes in a few minutes (I can even solve for initial conditions! What luxury!). Thanks again for taking the time to show me these spice tricks, I'm quite sure that I'll be using them for a while. \$\endgroup\$ – CoolNamesAllTaken Oct 2 '20 at 22:23
  • 1
    \$\begingroup\$ @CoolNamesAllTaken You're welcome! Don't forget that the schematic above will only work in LTspice, since it makes use of its built-in A-devices. Wherever you need switching elements, digital, SMPS-related, etc, these are the ones to go for the best performance and guaranteed convergence (for themselves, not for the rest...). \$\endgroup\$ – a concerned citizen Oct 2 '20 at 22:26
  • 1
    \$\begingroup\$ @CoolNamesAllTaken 1) It adds damping to avoid unwanted high frequency oscillations, but can be used as a crude approximation for core losses, too. The magnetizing inductance is taken care of automatically by the k L1 L2 1 statement. 2) It's one way to do it. It's also a lot to talk about, so try these three questions (and similar) for some more info. \$\endgroup\$ – a concerned citizen Oct 3 '20 at 7:21
  • 1
    \$\begingroup\$ Thanks for the explanation! That makes a lot of sense re: the resistance. I've read through the posts that you linked, and they were quite informative. Have a great weekend! \$\endgroup\$ – CoolNamesAllTaken Oct 4 '20 at 0:20

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