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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mult4X4 is
    Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
           y : in STD_LOGIC_VECTOR (3 downto 0);
           p : out STD_LOGIC_VECTOR (7 downto 0));
end mult4X4;

architecture Behavioral of mult4X4 is


component hadder is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           sum : out STD_LOGIC;
           cout : out STD_LOGIC);
          
end component hadder;

component fadder is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           cin : in STD_LOGIC;
           cout : out STD_LOGIC;
           sum : out STD_LOGIC);
end component fadder;


signal x0y1 : std_logic;
signal x1y0 : std_logic;
signal x2y0,x1y1,x0y2,x3y2,x2y3,x3y3 : std_logic;
signal x3y0, x2y1,x1y2,x0y3,x3y1,x2y2,x1y3 : std_logic;
signal c00,c01,c10,c02,c11,c20,c03,c21,c22,c32,c322 : std_logic ;
signal s1,s02,s2,s03,s13,s3,s04,s14,s4,s15,s5,s6,s7 : std_logic;

begin

x1y0 <= x(1) and y(0);
x0y1 <= x(0) and y(1);
 comp00: hadder  port map ( a => x1y0, b => x0y1, sum => s1, cout => c00 );

x2y0 <= x(2) and y(0);
x1y1 <= x(1) and y(1);
x0y2 <= x(0) and y(2);
 comp01: fadder  port map ( a=> x2y0, b => x1y1, cin => c00, cout => c01, sum => s02);
 comp10: hadder  port map ( a => s02, b => x0y2, sum => s2, cout => c10 );

x3y0 <= x(3) and y(0);
x2y1 <= x(2) and y(1);
x1y2 <= x(1) and y(2);
x0y3 <= x(0) and y(3);
 comp02: fadder  port map ( a=> x3y0, b => x2y1, cin => c01, cout => c02, sum => s03);
 comp11: fadder  port map ( a=> s03, b => x1y2, cin => c10, cout => c11, sum => s13);
 comp20: hadder  port map ( a => s13, b => x0y3, sum => s3, cout => c20 );
 


x3y1 <= x(3) and y(1);
x2y2 <= x(2) and y(2);
x1y3 <= x(1) and y(3);
comp03: hadder  port map ( a => '0' , b => x3y1, sum => s04, cout => c03 );
comp21: fadder  port map ( a=> s04, b => x2y2, cin => c11, cout => c21, sum => s14);
comp22: fadder  port map ( a=> s14, b => x1y3, cin => c20, cout => c22, sum => s4);

x3y2 <= x(3) and y(2);
x2y3 <= x(2) and y(3);
comp41: fadder port map ( a => c03, b => x3y2, cin => c21, cout => c32, sum=> s15);
comp42: fadder port map ( a => s15, b => x2y3, cin => c22, cout => c322, sum=> s5);

x3y3 <= x(3) and y(3);
comp32: fadder port map ( a=> c32, b=> x3y3, cin => c322, cout => s7,sum =>s6);

p(0) <= x(0) and y(0);
p(1) <= s1;
p(2) <= s2;
p(3) <= s3;
p(4) <= s4;
p(5) <= s5;
p(6) <= s6;
p(7) <= s7;


end Behavioral;

When I am trying to multiply 15 and 15 it shows the result as 209 and for larger number it shows different values.

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  • 2
    \$\begingroup\$ Shouldn't comp03 have ( a=> c02 ). You generated three carries int he prior adding stage but only used two of them. Otherwise c02 is never used. \$\endgroup\$ – user4574 Oct 2 at 6:28
  • 7
    \$\begingroup\$ how do you represent 16 with 4 bit data? \$\endgroup\$ – jsotola Oct 2 at 6:28
  • 2
    \$\begingroup\$ You haven't asked a question, nor shown how you expect it to work. Time to learn debugging. \$\endgroup\$ – Brian Drummond Oct 2 at 10:46
  • \$\begingroup\$ Sorry about that, I tried multiplying 15 X 15, the result was 209 instead of 225. \$\endgroup\$ – STARK_JR Oct 2 at 18:46
  • 2
    \$\begingroup\$ Then it isn't supposed to handle 16 * 2. Oh I see the edit. Map out what DOES work, what doesn't, and see if you can spot the pattern. An exhaustive testbench for such a small design is trivial. \$\endgroup\$ – Brian Drummond Oct 2 at 19:03
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Well since you confirmed my comment was actually the answer I will put it here.

comp03 should have ( a=> c02 ). You generated three carries in the prior adding stage but only used two of them. Otherwise c02 is never used

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