0
\$\begingroup\$

I want to find out what adder(ripple adder, carry look ahead adder etc.) does the operator + in verilog synthesize to when used in design an adder module. For example:

module fulladder(input logic input1, input2, c_in, output logic c_out, sum);
    assign {carry_out, sum} = input1 + input2 + c_in;
endmodule
\$\endgroup\$
3
  • \$\begingroup\$ This is not possible to answer unless you know what the data types of the wires are \$\endgroup\$ – Voltage Spike Oct 3 '20 at 5:38
  • \$\begingroup\$ Voltage Spike, I have added the data types as required. \$\endgroup\$ – user2987773 Oct 3 '20 at 15:04
  • \$\begingroup\$ There needs to be a size where you declared the wires \$\endgroup\$ – Voltage Spike Oct 3 '20 at 16:52
5
\$\begingroup\$

Depends on the tool and the target architecture.

It will sometimes for example infer a DSP48 (Xilinx) but that is not a given and sometimes you will get something built in the fabric (Which generally has a semi dedicated carry chain up a column, so this is quicker then you might expect).

Why do you even care as long as it meets timing?

If you want a particular design (again, why?) you can build it explicitly as a mess of combinatorial logic but that will generally be slower then letting the tool figure it out.

\$\endgroup\$
4
  • \$\begingroup\$ Thanks. I am required to provide justification for the use of + instead of using other operators such as & and |, used in the ripple carry adder design. \$\endgroup\$ – user2987773 Oct 2 '20 at 16:04
  • \$\begingroup\$ @user2987773 you could build it both ways and look at what the tool produces. \$\endgroup\$ – The Photon Oct 2 '20 at 16:13
  • 1
    \$\begingroup\$ The actual justification for using + is that it makes your intent clear to humans reading that HDL. Writing in a way that is clear for the maintenance programmer in 2 years time is usually more important then micro optimisation. Also, particularly with HDLs make sure you write in a way that matches your tools inference rules (Generally documented somewhere), if the tool identifies it as an adder (Which + is really helpful for) it will generally do a better job then if it just falls back on 'random combinatoric logic'. \$\endgroup\$ – Dan Mills Oct 2 '20 at 16:25
  • \$\begingroup\$ Also depends on the timing constraints. Push the constraints harder and you may get a larger but faster adder. \$\endgroup\$ – Brian Drummond Oct 2 '20 at 16:45
2
\$\begingroup\$

I want to find out what adder(ripple adder, carry look ahead adder etc.) does the operator + in verilog synthesize to when used in design an adder module.

The answer will depend on the synthesis target, and potentially also what the optimiser is optimising for.

In my experience on Altera FPGAs it will normally be a ripple carry adder, BUT said ripple carry adder will be implemented using the dedicated adder support in the FPGA fabric.

I am required to provide justification for the use of + instead of using other operators such as & and |, used in the ripple carry adder design.

The first reason is readability of the code, + is obviously an adder, some complex combination of basic logic operators is not. You could get around that to some extent by creating an adder module, but it's still more cumbersome than just putting a + in the code and someone still has to validate that the code in your adder module is correct. Generally when writing code you should not re-invent the wheel without a good reason.

The second reason is that basic building blocks on a FPGA are NOT simple gates, they are logic units of some kind. For example below is a (simplified) diagram of the "adaptive logic module" from a cyclone V.

As can be seen, this ALM has dedicated adder units with a dedicated carry chain. While this is a ripple carry adder, because it is implemented in dedicated logic it is likely to be much faster than a ripple carry adder implemented in generic logic.

Thus it is important that the synthesis tool recognizes that you adder is in-fact an adder. If you use the + operator the tool will know it's an adder from the start. If you use some other combination of logic then the tool may or may not figure out that you are building an adder.

\$\endgroup\$

Not the answer you're looking for? Browse other questions tagged or ask your own question.