I want to find out what adder(ripple adder, carry look ahead adder etc.) does the operator + in verilog synthesize to when used in design an adder module.
The answer will depend on the synthesis target, and potentially also what the optimiser is optimising for.
In my experience on Altera FPGAs it will normally be a ripple carry adder, BUT said ripple carry adder will be implemented using the dedicated adder support in the FPGA fabric.
I am required to provide justification for the use of + instead of using other operators such as & and |, used in the ripple carry adder design.
The first reason is readability of the code, + is obviously an adder, some complex combination of basic logic operators is not. You could get around that to some extent by creating an adder module, but it's still more cumbersome than just putting a + in the code and someone still has to validate that the code in your adder module is correct. Generally when writing code you should not re-invent the wheel without a good reason.
The second reason is that basic building blocks on a FPGA are NOT simple gates, they are logic units of some kind. For example below is a (simplified) diagram of the "adaptive logic module" from a cyclone V.
As can be seen, this ALM has dedicated adder units with a dedicated carry chain. While this is a ripple carry adder, because it is implemented in dedicated logic it is likely to be much faster than a ripple carry adder implemented in generic logic.
Thus it is important that the synthesis tool recognizes that you adder is in-fact an adder. If you use the + operator the tool will know it's an adder from the start. If you use some other combination of logic then the tool may or may not figure out that you are building an adder.